The Path Toward Efficient Nano-Mechanical Circuits and Systems

Transcription

1 The Path Toward Efficient Nano-Mechanical Circuits and Systems Tsu-Jae King Liu 1 Elad Alon 1, Vladimir Stojanovic 2, Dejan Markovic 3 1 University of California at Berkeley 2 Massachusetts Institute of Technology 3 University of California at Los Angeles November 3, nd Berkeley Symposium on Energy Efficient Electronic Systems

2 Proliferation of Electronic Devices Transistor Scaling Higher Performance, Investment Lower Cost Market Growth # DEVICES (MM) Source: ITU, Mark Lipacis, Morgan Stanley Research YEAR 2

3 Vision for 2020: Swarms of Electronics Infrastructional core Driver for More of Moore s Law Mobile access Driver for More Than Moore s Law Sensory swarm (trillions of devices) J. Rabaey, ASPDAC

4 Why Mechanical Switches? Relays have zero off-state leakage zero leakage energy 3-Terminal Switch Air gap Source t gap Gate Drain t dimple Relays switch on/off abruptly allows for aggressive V DD scaling (ultra-low dynamic energy) Drain Current 1.E-04 1.E-06 1.E-08 1.E-10 1.E-12 1.E-14 Measured I-V S 0.1mV/dec V RL V PI Gate Voltage 4

5 Outline Electro-Mechanical Relay Design for Digital ICs Relay-Based IC Design Relay Reliability Summary

6 4-Terminal Relay Structure Isometric View: Gate Oxide AA cross-section: OFF state Gate Drain A Body Drain Body insulator Source substrate Gate Body A Source AA cross-section: ON state Channel I DS A voltage is applied between the gate and body to bring the channel into contact with the source and drain. Folded-flexure design relieves residual stress. Gate oxide layer insulates the channel from the gate. R. Nathanael et al., IEDM

7 4-T Relay Process Flow (I) Mask 1: Electrode 80 nm Al 2 O 3 50 nm W Si substrate Mask 2: Contact dimple 100nm SiO 2 Mask 3: Channel 50 nm W 100nm 200nm SiO 2 40 nm Al 2 O 3 Deposit Al 2 O 3 substrate insulator ALD at 300 o C Deposit & pattern W electrodes DC magnetron sputtering Deposit 1 st sacrificial LTO LPCVD at 400 o C Define contact regions Deposit 2 nd sacrificial LTO Deposit & pattern W channel Deposit Al 2 O 3 gate oxide R. Nathanael et al., IEDM

8 Mask 4: Structure 4-T Relay Process Flow (II) SiO 2 1 m p+ poly-si 0.4 Ge 0.6 Deposit p+ poly-si 0.4 Ge 0.6 gate LPCVD at 410 o C Pattern gate & gate oxide layers using LTO as a hard mask HF vapor TiO 2 Release in HF vapor Coat with ultra-thin (~0.3nm) TiO 2 ALD at 300 o C R. Nathanael et al., IEDM

9 4-T Relay I D -V G Characteristic Plan View SEM of 4-T Relay 20 μm I DS (A) (a) 1E-02 1E-04 1E-06 1E-08 1E-10 1E-12 1E-14 V B = 9V V B = 0V V D = 2V V S = 0V V GS (V) Zero I OFF ; S < 0.1 mv/dec Hysteresis is due to pull-in mode operation (t dimple > t gap /3) and surface adhesion. R. Nathanael et al., 2009 IEDM / V. Pott et al., Proc. IEEE, Vol. 98, pp ,

10 See-Saw Relay Structure Plan View Close-Up of Channel Region Perfectly complementary operation is achieved in left and right channels V BL = 0 V; V BR = 10 V I DS (A) Measured I D -V G Characteristics 1E-03 1E-05 1E-07 1E-09 1E-11 1E-13 I DS_RIGHT V ON_RIGHT =V OFF_LEFT =3.16V I DS_LEFT L A =42μm L A1 =12μm W A =40μm V ON_LEFT =V OFF_RIGHT =7.14V 1E V G (V) J. Jeon et al., IEEE Electron Device Letters, Vol. 31, pp ,

11 See-Saw Relay Latch V WL SRAM Cell V CTRL Storage Node V SN NMOS V BL NMOS V DATA B L GND D L S L G D R S R Seesaw B R V DD V DATA (V) V CTRL (V) V WL (V) V BL (V) Demonstrated SRAM Cell Operation R = READ W = WRITE W '0' V DD =12V W '0' W '1' W '1' R '0' R '0' R '1' R '1' (b-a) (b-b) (b-c) (b-d) Time (s) J. Jeon et al., IEEE/ASME J. MicroElectroMechanical Systems, Vol. 19, pp ,

12 4-T Relay Turn-On Delay Turn-ON Time vs. Gate Voltage Turn-ON Time vs. Body Bias Turn-on delay improves with gate overdrive, and saturates at ~200ns for V B = 0V. Turn-on delay improves w/ body biasing to reduce V PI 100ns turn-on delay R. Nathanael et al., IEDM

13 Relay Scaling, Scaling has similar benefits for relays as for MOSFETs. Pull-in Voltage: V PI Relay Parameter A Scaling Factor Spring constant 1 / Mass 1 / 3 Pull-in voltage 1 / Pull-in delay 1 / Switching energy 1 / 3 k eff Device density 2 Power density 1 0 t 3 gap Pull-in Delay: t PI 65 nm Relay Design Parameter Value Actuation Area nm 2 Actuation Gap Dimple Gap Pull-in voltage Pull-in delay mt k eff dimple t gap V V PI DD 15 nm 10 nm 0.4V - 1V 100ns 10ns V. Pott et al., Proc. IEEE, Vol. 98, pp ,

14 Outline Electro-Mechanical Relay Design for Digital ICs Relay-Based IC Design Relay Reliability Summary

15 Digital IC Design with Relays 4 gate delays 1 mechanical delay CMOS: delay is set by electrical time constant Quadratic delay penalty for stacking devices Buffer & distribute logical/electrical effort over many stages Relays: delay is dominated by mechanical movement Can stack ~100 devices before t elec t mech Implement relay logic as a single complex gate F. Chen et al., ICCAD

16 Relay-Based VLSI Building Blocks 2010 ISSCC Jack Raper Award for Outstanding Technology Directions F. Chen et al., ISSCC

17 Technology Transfer to SEMATECH UC Berkeley: 1 µm litho 1st prototype: 120 µm x 150 µm SEMATECH: 0.25 µm litho Scaled relay: 20 µm x 20 µm 17

18 Energy-Delay Comparison with CMOS CMOS 30-stage FO4 inverter chain: 0 V V dd Output 30-relay chain: V dd 0 V 65 nm technology transition probability=0.01 cap/cmos inverter=0.57ff Input Output Scaled relay technology is projected to provide for >10x energy savings, at clock rates up to ~100MHz V. Pott et al., Proc. IEEE, Vol. 98, pp ,

19 Outline Electro-Mechanical Relay Design for Digital ICs Relay-Based IC Design Relay Reliability Summary

20 Stiction Hysteresis voltage (V PI -V RL ) scales with the pull-in voltage (V PI ) ignoring surface adhesion force Surface adhesion force scales with area of contacting region(s): Extracted from measured V PI,V RL I DS Relay I-V V RL V PI V GB H. Kam et al., 2009 IEDM 20

21 Contact Design for Logic Gates V DD R ON Mechanical Delay t PI ~ ns Electrical Delay t RC < 1 ps C L High R ON (up to ~10 kω) is acceptable To achieve good endurance and reliability: 1. Use hard electrode material Tungsten 2. Apply a surface coating to reduce surface force and current density ALD TiO 2 F. Chen et al., ICCAD

22 Contact Stability ON-state Resistance vs. # ON/OFF Cycles Contact resistance [Ω] 1.E+06 1.E+05 1.E+04 1.E+03 1.E k specification L=25 m Measured in ambient 1.E+0 1.E+3 1.E+6 1.E+9 No. of on/off cycles AFM Measurements Contact (a) Dimple FRESH CONTACT Never tested (c) Contact Dimple AFTER 10 9 cycles Variations are likely due to W oxidation No surface wear is seen after 1 billion ON/OFF cycles 3 μm 3 μm Relative distribution (a. i.) Relative distribution (a. i.) Dimple 19nm (b) Height 30 40(nm) 50 Height (nm) Dimple 19nm 19nm 19nm (d) Height (nm) H. Kam et al., IEDM 2009, R. Nathanael et al., IEDM

23 Relay Endurance Endurance increases exponentially with decreasing V DD, and linearly with decreasing C L Endurance is projected to exceed V H. Kam et al., IEDM

24 Nanoscale Relay Technology Sub-100 mv operation is possible Zero I OFF enables V DD scaling without increasing leakage power Hysteresis voltage scales with pull-in voltage Node (nm) Actuation Gap (nm) Pull-in Voltage (mv) Release Voltage (mv) * All dimensions scaled with technology node Source2 Drain2 Device Layout Source1 Drain1 Node (nm) Supply Voltage (V) Mechanical Delay (ns) Footprint for two switches = 14 14F 2 L. Hutin et al., to be published 24

25 Cross-Point Electro-Mechanical NVM Array Electro-mechanical diode cell design: Open circuit in Reset state Diode in Set state (built-in electric-field electrostatic force) SEM of NVM Array Cross-sectional SEM Current [A] 1E-04 1E-05 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 Measured I-V Set state Reset state Smallest cell layout area (4F 2 ); 3-D stackable Low-voltage operation Excellent retention behavior Multiple-time programmable (> 10,000 cycles) 1E V BL [V] W. Kwon et al., to appear in IEEE Electron Device Letters 25

26 Outline Electro-Mechanical Relay Design for Digital ICs Relay-Based IC Design Relay Reliability Summary

27 Summary Mechanical switches have the ideal properties of zero off-state leakage and abrupt turn-on/turn-off. potential for achieving very low E/op (<1 aj) Dimensional scaling is required to achieve low-voltage operation and adequate reliability V DD < 100 mv endurance > cycles Materials optimization can yield further improvements. New circuit and system architectures are needed to fully realize the potential energy-efficiency benefits. device and circuit design co-optimization is key! 27

28 Acknowledgements NEM-Relay Team (current and former) members: Post-docs: Louis Hutin; Hei Kam (now with Intel); Vincent Pott (now with IME, Singapore) Students: Rhesa Nathanael, Jaeseok Jeon (now with Rutgers U.), I-Ru Chen, Yenhao Chen, Jack Yaung, Matt Spencer; Fred Chen and Hossein Fariborzi (MIT); Chengcheng Wang and Kevin Dwan (UCLA) Funding: DARPA/MTO NEMS Program DARPA/MARCO Focus Center Research Program Center for Circuits and Systems Solutions (C2S2) Center for Materials, Structures, and Devices (MSD) NSF Center of Integrated Nanomechanical Systems (COINS) NSF Center for Energy Efficient Electronics Science (E3S) UC Berkeley Micro/Nanofabrication Laboratory 28

29 Frequently Asked Questions 1. Displacement (x) due to gravity? x mg k eff 0.1fm 2. Mechanical shock causing pull-in? requires acceleration > 10 6 g due to small m (10-14 grams) 3. Thermal vibration? 1 2 k 1 2 BT k 2 eff x x 1Å for T = 300K 29