Fabrication and Characterization of Emerging Nanoscale Memory
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1 Fabrication and Characterization of Emerging Nanoscale Memory Yuan Zhang, SangBum Kim, Byoungil Lee, Marissa Caldwell(*), and (*) Chemistry Department Stanford University, Stanford, California, U.S.A. Center for Integrated Systems
2 Non-Volatile Memory Technology Research Initiative (NMTRI) at Stanford University I TEXAS NSTRUMENTS 2
3 Memory In Your Hands (~2010) C. Kim, Future Memory Technology: Trends and Challenges, Plenary paper, ISQED (2006). 3
4 Outline Opportunities for emerging memories Study of phase change nanodots NiO Resistance change memory Beyond the memory cell Integration of nanowire selective diode with phase change memory cell Summary 4
5 Memory Market: DRAM and Flash Dominate 80 Billions of Dollars 60 Flash DRAM Ref: isuppli, 3Q 2006 Other Memory Other Non-volatile Memory NOR NAND SRAM DRAM Source: Gary Bronner (Rambus), Stanford EE 309 lecture, Fall
6 Phase Change Memory Basic Structure: Operation Principle: Device operates by switching between low resistance SET state and high resistance RESET state. Phase change principal: V + Switching behavior: 6 S. Lai, H.-S. "Current Philip Wong status of the phase change memory and its future," IEDM Tech. Dig., pp , December Department of Electrical Engineering
7 Reset Current Reduction Reducing reset current is one of the most important issues of phase change memory Reduce contact area (brute force) Engineer the device structure to achieve highest heating for a certain current Engineer the interface thermal and electrical resistance of the GST / electrode interface Engineer the electrical and thermal properties of the phase change material 7
8 Reset Current Reduction Needed Typical high performance transistor drive current ~ 1mA/μm At 32 nm, for W/L=4, I=128 μa I RESET = 128 μa 8 Diameter = 18 nm (S. Lai et al.) A. Pirovano, A. L. Lacaita, A. Benvenuti, F. Pellizzer, S. Hudgens, and R. Bez, "Scaling analysis of phase-change memory technology," IEDM Tech. Dig., pp , December 2003.
9 Phase Change Nanodot by Self-Assembly Diblock copolymer PS-PMMA template and lift-off process PS hole size distribution 0.2 Diameter fitting curve AIST nanodots Density Mean: ~18.5nm Sizes of PMMA Holes (nm) 200nm 200nm 9 Y. Zhang, S. Raoux, D. Krebs, L.E. Krupp, T. Topuria, M. Caldwell, D.J. Milliron, P.M. Rice, J. Jordan-Sweet, H.- S. P. Wong, Crystallization Characteristics of Phase Change Nanoparticle Arrays Fabricated by Self-Assembly Based Lithography, Materials Research Society (MRS) Symposium, San Francisco, CA, USA, paper G8.5, March 24 28, 2008
10 Stanford University nm Phase Change Nanodots Ge2Sb2Te5 GeSb AIST (AgInSbTe) 200nm GeSb AIST Y. Zhang, S. Raoux, J. N. Cha, L. E. Krupp, C. T. Rettner, H.-S. P. Wong, Transition Behavior of High Density Ordered Phase Change Nanostructure from Diblock Copolymer Template, MRS Spring Meeting, Symposium I, paper I-12.8, April 10-12, San Francisco,
11 XRD Results of GeSb Nanodots 15nm film 2.5nm film Thin film (003) (003) nanodots (003) Nanodots (012) Nanodots start to crystallize at much higher temperature than blanket films. Y. Zhang, S. Raoux, D. Krebs, L.E. Krupp, T. Topuria, M. Caldwell, D.J. Milliron, P.M. Rice, J. Jordan-Sweet, H.-S. P. Wong, Crystallization Characteristics of Phase Change Nanoparticle Arrays Fabricated by Self-Assembly Based Lithography, Materials Research Society (MRS) Symposium, San Francisco, CA, USA, paper G8.5, March 24 28,
12 XRD Results of GST Nanodots 15nm film (004) 3.6nm film (004) nanodots (111) (101) (101) (101) (200) For thicker film, crystallization transit into fcc phase at 160 o C, and hcp phase at 380 o C. For thin film, the transition is directly into rhombohedral phase at 350 o C. For nanodots, the fcc phase transition does not happen, consistent with very thin GST blanket film. Y. Zhang, S. Raoux, D. Krebs, L.E. Krupp, T. Topuria, M. Caldwell, D.J. Milliron, P.M. Rice, J. Jordan-Sweet, H.-S. P. Wong, Crystallization Characteristics of Phase Change Nanoparticle 12 Arrays H.-S. Fabricated Philip Wong by Self-Assembly Based Lithography, Materials Research Society (MRS) Symposium, San Francisco, Department CA, USA, of paper Electrical G8.5, March Engineering 24 28, 2008
13 Metal Oxide M-I-M Memory Motivation: Low programming voltage (< 3V) Low programming current Uni-directional programming Easier to build cross-point array Material set compatible with conventional semiconductor processing (e.g Ni) Key issues: Physics of resistive switching Device scaling properties 13
14 NiO Microstructure 200 nm Pt NiO Pt Columnar grains D.C. Kim, M.J. Lee et al., Improvement of resistive memory switching in NiO using IrO 2, Appl. Phys. Lett., Vol. 88, p (2006) B.I. Lee, H.-S. P. Wong, unpublished. 14
15 Fabricated Structure Pt NiO Pt SiO 2 Si Cross-section < Schematic of the fabricated structure. NiO thickness = 20nm > 15
16 Beyond The Memory Cell Cell selection device for crosspoint memory 16
17 Cross-Point Memory Cell Selection Device Requirements: Stackable, low temperature processing Enough current drive for programming Unidirectional and (ideally, bi-directional) programming BL n-1 BL n BL n+1 BL n-1 BL n BL n+1 V/2 0 WL m+1 WL m Leakage current V Selected cell WL m+1 WL m V Selected cell V/2 Half-Selected cell 0 WL m-1 WL m-1 V/2 0 V/2 Without Diode V 0 V With Diode 17
18 Oxide Diode For 3D Stacking of Crosspoints TE Binary Oxide BE P-type oxide N-type oxide Silicon or Oxide Diode - Uses NiO as p-type, TiO 2 as n-type semiconductor with φ50um.(~10 2 A/cm 2 ) - Process temperature < Current density needs to be increased by a few orders for reasonably small OxRRAM cells. Oxide diode property Binary oxide switching 10-1 Switching combined with oxide diode Current (A) Voltage (V) Current (A) Source: S. Seo (2006) On state Off state Voltage (V) Current (A) On state Off state Voltage (V) 18
19 Cross-Point Memory Array with Selective Nanowire Diode Bitline (B/L) SL SL m+1 SL m-1 WL WL n WL n n WL WL n Memory element WL n-1 WL n n WL WL n Nanowire diode Top electrode WL n Bottom electrode WL n+1 n Diode plus memory element Wordline (W/L) Y. Zhang, S. Kim, J.P. McVittie, H. Jagannathan, J.B. Ratchford, C.E.D. Chidsey, Y. Nishi, and H.-S. P. Wong, An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory, Symp. VLSI Technology, pp , June 12 14, 2007, Kyoto, Japan. 19
20 Nanowire Bottom Electrode Small diameter electrode, reduces programming current Route to pn-junction diode selection device Low-temperature (<350C) nanowire synthesis 40nm N-type Ge nanowire 100nm TiN 25nm GST Ge nanowires 200nm SiO2 SiO2 P-type Si (111) Si Substrate Y. Zhang, S. Kim, J.P. McVittie, H. Jagannathan, J.B. Ratchford, C.E.D. Chidsey, Y. Nishi, and H.-S. P. Wong, An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory, Symp. VLSI Technology, pp , June 12 14, 2007, Kyoto, Japan. 20
21 Nanowire Diode + Phase Change Memory I forward (ua) µm 5µm 2µm 1µm 500nm V forward (V) Y. Zhang, S. Kim, J.P. McVittie, H. Jagannathan, J.B. Ratchford, C.E.D. Chidsey, Y. Nishi, and H.-S. P. Wong, An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory, Symp. VLSI Technology, pp , June 12 14, 2007, Kyoto, Japan. 21
22 Repetitive Pulse SET/RESET Programming 100M V READ =3V Programming Current RESET : 173µA SET : 45.5µA R (Ω) 10M 1M Times 2µm 2µm pad size Pulse conditions RESET : 8.5V 5ns/1µs/5ns SET : 5.5V 100ns/20µs/100ns * type : amplitude(v) rising time /pulse width / falling time Current (A) 2.0x x x x10-5 Programming Current Times Y. Zhang, S. Kim, J.P. McVittie, H. Jagannathan, J.B. Ratchford, C.E.D. Chidsey, Y. Nishi, and H.-S. P. Wong, An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory, Symp. VLSI Technology, pp , June 12 14, 2007, Kyoto, Japan. 22
23 Conclusions 23 New materials enable new memory devices Plenty of new materials, difficult to satisfy memory requirements Scalability is a key issue Material property, stackable, small cell size, multi-bit/cell Nanofabrication techniques has been applied to study nano-scale memory device characteristics Nanocrystal synthesis and diblock copolymer method for sub- 20nm phase change nanodots Ebeam lithography for sub-100nm NiO memory arrays Nanowire diode as selection device for PCM cell Future applications will be enabled by new memory technologies
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