CMOL: Hybrid of CMOS with Overlaid Nanogrid and Nanodevice Structure. John Zacharkow

Transcription

1 CMOL: Hybrid of CMOS with Overlaid Nanogrid and Nanodevice Structure John Zacharkow

2 Overview Introduction Background CMOS Review CMOL Breakdown Benefits/Shortcoming Looking into the Future

3 Introduction CMOS transistor density has doubled every 18 months since early 70s

4 Introduction CMOS is reaching its scaling limits Cost increasing exponentially 90nm lithography mask ~ $800,000 65nm mask ~ $1.2 million 45nm mask ~ $2 million

5 Introduction Current alternative: Multi-core processors Numerous research and development efforts into other alternatives Non-classical CMOS layout Alternate state variables Alternate transistors (ex: molecular)

6 Introduction CMOL: A hybrid of CMOS with overlaid nanogrid of nanowires and nanodevices

7 CMOS Review Fabrication

8 CMOS Review Fabrication

9 CMOS Review Function V in V+ V out has mobile carrier electrons has holes Electrons must flow towards source for current to pass from source to drain

10 CMOS Review Problems Scaling Limitations Smaller insulator cannot insulate as well Counter with smaller input voltage Transistors more difficult to control At small enough size, gate control virtually impossible Will hit CMOS scaling limit around nm gate length

11 CMOL Nanogrid layer of wires and nanodevices on top of CMOS stack increases transistor density increased communication of CMOS elements

12 CMOL Overview Nanodevice at each junction

13 CMOL Nanodevices Favorable candidate for nanodevice is binary latching switch two terminal, bistable device

14 CMOL Nanodevices Binary latching switch Consists of drain, source, and single electron transistor and trap Evaluate for both OFF and ON positions

15 CMOL Nanodevices OFF Drain-to-source voltage below voltage threshold V+ Trap island net charge (Q=-ne) is zero Transistor island blocks flow of current because of Coulomb Blockade

16 CMOL Nanodevices ON Drain-to-source voltage above voltage threshold V+ V s, through capacitance C s, alters potential of trap Causes an electron to tunnel into trap Change in trap charge alters potential of transistor Lowers coulomb blockade threshold below V+

17 CMOL Nanowires Placement Interface pins Two levels of perpendicular nanowires

18 CMOL Nanowires Pins could be made using similar method to those produced for field emitter arrays Scale bar = 2µm Scale bar = 1µm

19 CMOL Nanowires Placement - Nanodevice turned ON by voltage ±2V W - Perpendicular nanowires have ±V W applied - Only nanodevice at junction will see ±2V W and be activated

20 CMOL Nanowires Rotation of nanogrid by angle α allows unique access of a CMOS cell to the cells around it through nanostructure α = arcsin(f nano /βf CMOS ) F CMOS = half-pitch of CMOS cell F nano = half the distance between nanowires

21 Benefits and Downsides Benefits Much greater device densities and speeds are possible Densities as high as (1 trillion) per cm 2 Speeds up to operations/second Intel s 32nm (not commercially produced) chip billion transistors Current 45nm quad-core processor million transistors

22 Benefits and Downsides Embedded memory or stand-alone memory chips Nanodevice: single bit memory cell CMOS substructure: perform coding, decoding, input/output functions, and other necessary tasks Currently, too many defects

23 Benefits and Downsides Downsides Defect-free fabrication currently out of reach Nanowires Photolithography not fine enough resolution Direct electron beam lithography and scanning-probe manipulation output not great enough Carbon nanotubes and other self-assembling structures Cannot be accurately placed on interface pins Nanoimprint and interference lithography New, may in future provide necessary resolution

24 Benefits and Downsides Downsides Nanodevices No group has achieved successful self-assembly of such devices on pre-fab electrodes Ones that conduct differ in I-V curves Devices get turned ON when they shouldn t Devices don t get turned ON at all

25 Looking to the Future CMOL will be very attractive when fabrication is feasible Extend Moore s Law years Scalability limited by quantum-mechanical tunneling between nanowires Tunneling becomes apparent at F nano = 2nm Safely say minimum F nano = 3nm for CMOL

26 References C. A. Spindt. Microfabricated Field Emitter Arrays. Menlo Park, CA. Copyright 2005 Microscopy Society of America. K. K. Likharev. CMOL and cousins: Hybrid CMOS/nano circuit FAQs. Stony Brook University, Stony Brook, NY. K. K. Likharev and D. B. Strukov. CMOL: Devices, Circuits, and Architectures. Stony Brook University, Stony Brook, NY. K. K. Likharev and D. B. Strukov. A Reconfigurable Architecture for Hybrid CMOS/Nanodevice Circuits. Stony Brook University, Stony Brook, NY. X. Ma, D. B. Strukov, J. H. Lee, and K. K. Likharev. Afterlife for Silicon: CMOL Circuit Architectures. Stony Brook University, Stony Brook, NY. First 45nm Intel Core Microarchitecture. Intel. 31 March [ Global Semiconductor Industry Faces the Limits of Photolithography and the Emergence of New Technologies. 5 July BNet Business Network. 31 March [ The History of the Integrated Circuit. 5 May Nobelprize.org. 31 March [

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