1 Introduction

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1 Published in Micro & Nano Letters Received on 9th April 2008 Revised on 27th May 2008 ISSN Design of a transmission gate based CMOL memory array Z. Abid M. Barua A. Alma aitah Department of Electrical and Computer Engineering, University of Western Ontario, London, Canada zeabid@eng.uwo.ca Abstract: A design of a nanoelectronic memory array, compatible with both the molecular switch (nanodevice) electrical characteristics and CMOS 45 nm semiconductor technology node is presented. The proposed transmission gate based CMOL (hybrid CMOS/MOLecular) memory cell does not suffer from the operational difficulties faced by the conventional CMOL cell. The control circuitry with improved multiplexer designs is introduced, and it shows that the required voltage levels to program the nanodevices can be achieved. Moreover, the proposed memory cell has the same area as the existing CMOL inverter cell allowing easier implementation of both logic and memory circuits on the same chip. 1 Introduction Silicon technology continues to advance towards the end of Moore s Law, predicted with the end of CMOS (complementary metal oxide semiconductor) scaling, only years away. Consequently, a number of nanodevices such as single electron transistor (SET), resonant tunnelling devices (RTD), carbon nanotubes and molecular electronics are proposed as promising candidates for the next-generation nanoelectronics technology [1, 2]. There is a strong interest in new, molecular-scale devices that might complement the basic silicon platform by providing it with new capabilities or that might even replace silicon technology and allow device scaling to continue to the atomic scale [3]. Among all the promising candidates for the next-generation nanoelectronics technology, CMOL is considered for the combination of the advantages of CMOS technology (including flexibility and high fabrication yield) with the extremely high density and programmable molecular-scale two-terminal nanodevices. CMOL-based memory cells offer high density, programmability and easy configuration, along with high defect tolerance capabilities based on the nanodevice properties [1, 4]. The CMOL structure is based on the combination of a traditional CMOS stack, having a nanowire crossbar structure, with molecular electronic devices at the crossbar intersection points [5 7]. A single CMOL inverter cell and the approach to select a nanodevice are shown in Fig. 1. The programmable molecular nanodevices formed between the nanowires, with charge storage properties, may be used as nanoscale memory devices. The nanodevice provides diode like I-V curves for logic circuit operations and allow circuit mapping on CMOL fabric [8]. The possibility to reconfigure the nanodevice after fabrication makes this approach even more valuable than the leading CMOS technology. On the basis of the CMOL concept, terabit scale memory was proposed [9] using traditional crossbar memory structure. An analysis of the CMOL geometry shows that each nanowire segment stretches over r CMOS cells and contacts r 2 crosspoint nanodevices [9]. Because of the difference in its cell structure to the CMOL logic cell (inverter cell), design and fabrication of any logic and memory circuit on a single chip will be complicated. The use of pass transistors to pass/transmit a voltage signal, through a pin, to the nanodevices through the nanowires has its limitations as explained in Section 3. To overcome all of this complexity, a transmission gate based CMOL memory cell along with its improved control circuit is proposed and presented in the following sections. 70 Micro & Nano Letters, 2008, Vol. 3, No. 3, pp

2 Figure 1 Single CMOL inverter cell and the approach to select a nanodevice a CMOL inverter cell [5] b Addressing a particular nanodevice [5] 2 Nanodevice properties The nanodevice in CMOL is a binary latching switch based on molecules with two metastable internal states. Fig. 2 shows the I-V characteristics of a typical single electron-latching switch. Different combinations of organic molecules, with varying electrical behaviours and molecular structure, have different operational voltages [10 13]. In the OFF state the device passes almost no current until the applied voltage reaches a certain threshold value V t (þ). At this point, the device switches to ON-state with a finite current. The switching to OFF-state takes place at voltage V t (2). In the lowresistive state representing (bit 1), the nanodevice is essentially a diode, so that the application of voltage V C, V READ, V t (þ) to the top nanowire leading to the memory cell gives substantial current injection into the bottom wire (connected to ground). This current pulls up the output voltage that can be read out by a sense amplifier. In the OFF state (bit 0) the current through the molecular switch is very small, giving a nominally negligible contribution to the output signal at readout. In order to switch the nanodevice to ON state (i.e. write bit 1), the two nanowires leading to the device are fed by voltages V WRITE(þ) and V WRITE(2), with V WRITE(þ), V t (þ), V WRITE(þ) þjv WRITE(2) j Figure 2 I-V Characteristics of a single molecular switch [14] (this ensures that the operation does not disturb the state of semi-selected devices contacting just one of the biased nanowires). The write 0 operation is performed similarly by reversing the applied voltages with [jv WRITE(2) j, jv t (2)j, V WRITE(þ) þjv WRITE(2) j] (Fig. 2). We chose 1.6 V (¼V WRITE(þ) þjv WRITE(2) j) for ON-state (write 1), 21.6 V for OFF-state (write 0), and 1 V for read operation using single bipyridyl-dinitro oligo-phenylene ethynylene dithiol (BPDN-DT) as the nanodevice [10]. The minimum voltages, across this nanodevice, to write bits 0 and 1 are V t (2) ¼ 21.3 V and V t (þ) ¼1.3 V (Fig. 2), respectively [10]. 3 Operation limitations of previous memory cell designs HSPICE simulations were first performed on single PMOS and NMOS transistors to check the pass transistor behaviour by applying a sinusoidal voltage (V in ) of 1 V amplitude at its source/drain (S/D) terminal. MOSFET models, based on Berkeley predictive technology [15], were used in our circuit simulation, representing the future 45 nm CMOS technology [16]. In the positive cycle, with the gate voltage V g ¼ 1 V, the output voltage level V out dropped to 0.7 V (known as threshold voltage loss [17]). The turning-on of the pn junction between the S/D and substrate occurs for V in,20.6 V since the body of the NMOS is connected to ground resulting in the deterioration of the transmitted signals. PMOS can pass a high voltage level without any losses (strong logic 1). However, for low input voltages, 21V, V in, 0.3 V, with the gate voltage V g ¼ 0 V, the output voltage is degraded and stays constant (V out ¼ 0.3 V) due to threshold voltage loss and the turning-off of the PMOS transistor for negative input signals. Therefore, applied voltages (V in ) have to be restricted to the range of [20.6, þ0.7 V] for NMOS (with V g ¼ 1V) Micro & Nano Letters, 2008, Vol. 3, No. 3, pp

3 and [þ0.3 V, þ1.6 V] for PMOS (with V g ¼ 0 V). If transmission gates (TG) are used, a range of [20.6 V, 1.6 V] is possible. The NMOS body is assumed to be connected to ground, whereas the body of the PMOS is connected to V dd (¼1.0 V). However, if the NMOS and PMOS are biased with V g ¼ 0 V and 1 V, respectively, so that they are turned-off, then the restriction becomes even tighter allowing V in.20.3 V for NMOS and V in, 1.3 V for PMOS assuming that their threshold voltage jv t j ¼ 0.3 V. Consequently, we chose (1.2 V and 20.4 V) as the two reference voltages to turn the nanodevice ON and OFF while allowing normal operation of NMOS and PMOS transistors. However, using V in ¼ 20.4 V instead of V in.20.3 V, the NMOS is ON instead of being OFF for V g ¼ 0 V and a design that overcomes such a drawback will be presented. The nanowire s equivalent resistance and capacitance are calculated by considering a single-cell area A cell ¼(2bF CMOS ) 2 ¼ mm 2, F cmos ¼ half pitch of the CMOS subsystem ¼ 22.5 nm, b (dimensionless factor depends on CMOS cell complexity) ¼ 4 and half pitch of the nanowire F nano ¼ 4.5 nm [1]. A 1.8 mm long nanowire s equivalent resistance (R w ) and capacitance (C w ) are 1 kv and 0.36 f F, respectively. Single-molecule (BPDN-DT) ON and OFF states have equivalent resistances of and V, respectively [10]. For self-assembled monolayers, the footprint of a single molecule is 0.25 nm 2 [8]. So the number of molecules per cross point is F 2 nano/ 0.25 ¼ 81, resulting in ON and OFF resistances of R ON ¼ V and R OFF ¼ V. Circuit simulations (HSPICE) were performed, using 45 nm CMOS technology [16] based on Berkeley predictive technology [15], on the equivalent circuit of previous memory cell designs where (NMOS) pass transistors are used (Fig. 3). Simulation results show that applying 1.2 and 20.4 V as V 1 and V 0, a voltage of 1.3 V across the nanodevice (R ON/OFF ) during the ON and OFF operation is recorded, even for various values of V dd (applied as RS), V t (transistor threshold voltage) and R ON (of the nanodevice) as shown in Fig. 4. The pass transistors poor transmission of the signals V 1 and V 0 causes this effect. The nanodevice state (ON/OFF) cannot be changed by these voltages since they fall within the Coulomb blockade range (21.3 to þ1.3 V, Fig. 2) [10]. These are the operational difficulties Figure 4 Voltage drop across the nanodevice of the conventional CMOL memory cell (based on pass transistor PT), varying the threshold voltage (V t ), the voltage (V dd ) and the nanodevice resistance (Ron) of the conventional CMOL circuits and an improved design is proposed is the next section. More simulation results, comparing the conventional and the proposed memory cells, will be presented in the next section. 4 Proposed memory cell design Pass transistors are unable to pass the required voltage to program the nanodevices as explained above. In our proposed CMOL memory cell, we use transmission gates (TG) where the PMOS and NMOS combination can pass the required positive and negative voltages. TGs were previously used to design two new CMOL cells (T- and I-cells) to allow the implementation of sequential logic circuits [18] but not single-cell memory. Fig. 5 shows the diagram of the proposed CMOL memory cell. CMOS rows 1 and 2 can be selected using a selection signal RS and its inverse. The RS signal is used to switch- ON and OFF the transmission gates. CMOS columns 1 and 2 are used to pass the required voltage to the nanodevice through the TG. Fig. 6 shows the equivalent circuit of the proposed TG-based single memory cell. To switch the device ON, a voltage.1.3 V needs to be applied across the nanodevice (R ON/OFF ). This is achieved by applying the voltages V1 ¼ þ1.2 V and V 0¼ 20.4 V through the TG, with RS voltage being V dd ¼ 1V. Consequently a maximum voltage close to 1.6 V appears across the nanodevice. To switch-off the device, the applied voltages V 1 and V 0 are reversed. Figure 3 Equivalent circuit of current CMOL memory cell 72 Micro & Nano Letters, 2008, Vol. 3, No. 3, pp

4 Figure 5 Proposed CMOL memory cell Fig. 7 shows a comparison between the performance of the conventional CMOL memory cell (PT) and the proposed CMOL cell (TG), in CMOS 45 nm technology node, with V dd ¼ 1 V. The correct operation of the proposed cell and its robustness against the variability of the transistor threshold voltage V t ( V) and for various values of R ON ( MV) and V dd ( V) are clearly in contrast to the PT based cells. The nanowire s resistance and capacitance were also varied, R w ¼ KV and C w ¼ f F, but did not have a significant effect on the measured voltage drop across the nanodevice. Power dissipation simulations were also conducted confirming the lower power operation of TG CMOL cells compared with the PT designs. However, since the PT cell is not operating properly, such comparison is not meaningful. Figure 7 Voltage drop (across the nanodevice) comparison between the PT and TG memory cells with variations in the threshold voltage V t and the nanodevice resistance (R on ), V dd ¼ 1V Fig. 8 presents similar comparisons but for the 32 nm CMOS technology node. The assumed nanowire R w and C w are kv and ff. The values of R ON were chosen based on the lower number of molecules expected at each nanowire crossover, as the CMOS cell is smaller for the 32 nm CMOS node, resulting in a higher value of the resistance (R ON ). A similar conclusion is also reached where the PT memory cell is not operating properly since the voltage across the nanodevice did not reach or exceed the required 1.3 V. This is in contrast to the proposed design where the applied voltages V 1 and V 0 do appear across the molecular nanodevice and consequently lower V 1 (by up to 0.2 V) could be used at the expense of less tolerance to process variations. The proposed CMOL memory cell was also tested for the 22 nm CMOS node (Table 1). The assumed nanowire R w and C w are kv and ff. The value of R ON was computed based on the lower number of molecules per nanodevice compared with the 45 and 32 nm CMOS Figure 8 Nanodevice voltage drop for the PT and TG memory cells for variable threshold voltage V t,andtwo values of R ON (nanodevice) and V dd (R S signal). 32 nm CMOS node is used Table 1 Voltage drop across the nanodevice of each of the two CMOL memory cells (PT and TG), using 22 nm CMOS technology node R on,mv V dd, V Previous (PT) cell, V Proposed (TG) cell, V V1 and V0 were assumed as 1.2 and 20.4 V Figure 6 Equivalent circuit of the proposed CMOL memory cell and its symbol Micro & Nano Letters, 2008, Vol. 3, No. 3, pp

5 Figure 9 CMOL memory array with the control circuit Figure 10 TG-based and the proposed multiplexers a TG-based multiplexer b Proposed multiplexer nodes. Consequently higher values of R ON (37.4 MV and 1.10 MV) were used in the simulations. The operational difficulties of the PT cell were also observed, confirming the need of the proposed design. The proposed TG memory cell operates properly under all simulated conditions, for the three CMOS technology nodes (45, 32 and 22 nm), reflecting the robustness of the proposed design even under the variability of the threshold voltage V t, the nanodevice resistance R ON and V dd. Power dissipation was measured for various simulation conditions indicating the superiority of the TG cell. However, the results are not presented since the PT cells did not operate properly and the molecular nanodevice cannot be Figure 11 Equivalent circuit of the proposed memory cell with: a An improved control circuit b A further simplified control circuit programmed under the simulated conditions for all three technologies. 5 Design of the control circuit The two reference voltages 1.2 and 20.4 V, as V 1 and V 0in Fig. 9, were chosen to turn the nanodevice ON/OFF with some margins for process variability, due to the nature of (2) nano fabrication, of molecular switches (R ON, V t and V (þ) t, see Fig. 2) and the MOSFET transistors (PMOS and NMOS) threshold voltage (V t ). These voltages are within the Coulomb-blockade range (21.3 to þ1.3 V), and consequently the unselected devices will not be affected. These two voltage levels (1.2 and 20.4 V) are the best combination as more positive or negative voltages either violate the conditions V 1, 1.3 V and V 0, 1.3 V, needed to avoid unwanted Write operation, or turn-on the Table 2 Comparison of the above two multiplexers with input signals: V0 ¼ 20.4 V, V1 ¼ 1.2 V Type of MUX Output voltage Y, fors ¼ 1, V Output voltage Y, fors ¼ 0, V Power, W Time delay, ps TG based MUX t HL ¼ 10 t LH ¼ 13 proposed MUX t HL ¼ 10 t LH ¼ Micro & Nano Letters, 2008, Vol. 3, No. 3, pp

6 Table 3 Simulation results of the memory cell including its control circuits Molecular nanodevice (switch) operation Power, mw Memory cell with modified MUX (Fig. 11a) Time delay, ps Nanodevices voltage drop, V Power, mw Memory cell with simplified MUX (Fig. 11b) Delay, ps Voltage drop across the nanodevice, V ON to OFF a OFF to ON a þ þ1.55 ON to OFF b OFF to ON b þ þ1.56 a Set-1: The width W of each transistor is fixed to 10l b Set-2: Series NMOS transistor W n ¼ 20l; all PMOS transistors W p ¼ 30l; the remaining NMOS transistors W n ¼ 10l PMOS/NMOS transistors. A value of V in ¼ V s.1.4 V, with V g ¼ 1 V, causes V gs V t turning the PMOS ON. Similarly, V in ¼ V s,20.4 V and V g ¼ 0 V cause NMOS to be ON (since V gs V t and a threshold voltage jv t j ¼ 0.3 V is assumed). However, for V g ¼ 0V and V in ¼ 20.4 V, the NMOS is supposed to be OFF but is ON since V gs ¼ þ 0.4 V.V t and consequently this issue needs to be addressed and a solution is required. A CMOL memory array with its control circuits is shown in Fig. 9. V R ¼1 V is the voltage used for READ operation. The Read sensor circuit is not shown, it will be connected to the CMOS column 2 (Fig. 5) and the stored bit can be recognised by sensing the ON and OFF currents. The required ON/OFF voltages, transmitted to the device through the cell s transmission gates, are selected by the control circuits connected with the top and bottom nanowires. A tansmission gate based multiplexer (Fig. 10a), to pass positive and negative reference voltages (V 1 and V 0) based on the selection signal (S), is used. Fig. 10a shows the general schematic diagram of the multiplexer. However, a voltage of V0 (20.4 V) turns the NMOS partially-on, instead of being OFF, causing a degraded output voltage (0.3 V drop, see Table 2) due to the leakage current of the partially ON NMOS. To improve the multiplexer circuit, we added a series NMOS (Fig. 10b) to the transmission gate connected with V 0, which forces the series NMOS into cutoff region when S ¼ 1. Table 2 shows the comparison between the performance of the TG-based and the proposed multiplexer. Power dissipation can be reduced by 56% due to the proposed multiplexer, at the expense of a larger time delay (t LH )of the output signal (Y ) switching from low to high. Fig. 11a shows the memory cell with the proposed control circuits, and Fig. 11b shows the design of a further improved (simplified) control circuit. This is achieved knowing that the PMOS transistor transmits the high-level signals V 1 and VR well so the TG is replaced with a simple PMOS. Also, the series NMOS transistors transmit better low-level signals (V 0) so the PMOS can be removed. Table 3 shows the simulation results comparison between the proposed memory cell (Fig. 5) with these two different control circuits (Figs. 11a and Figs. 11b) using a selection signal (RS) frequency of 50 MHz. Two different sets of MOS transistor width (W ) are used to increase the speed and the voltage drop across the nanodevice. Set 1 uses the same width for all transistors, W ¼ 10l. Set 2 uses larger PMOS transistors (W ¼ 30l)and larger series-nmos transistors (W ¼ 20l). Increasing the transistors width improved slightly the final voltage, for Write operation, across the nanodevice by up to 0.03 V (2%) and decreased the time delay by up to 34% at the expense of higher power dissipation (up to 93%). 6 Area analysis Our proposed memory cell needs four transistors (two transmission gates), similar to the existing CMOL inverter cell [4], so the proposed memory cell can be fabricated within the same area as CMOL inverter cell. This will simplify the fabrication process as well as the implementation of some logic and memory-integrated circuits on the same chip. 7 Conclusion The proposed CMOL memory cell overcomes the limitations of the existing CMOL cell used for memory arrays. The TG memory cell operates properly under all the simulated conditions, for the three CMOS technology nodes (45 nm, 32 nm and 22 nm), conforming its robustness even the under variability of various parameters (threshold voltage V t, nanodevice resistance R ON and the selection signal voltage V dd ). The PT cells did not operate properly since the molecular nanodevice could not be programmed or reconfigured under the simulated conditions for all three CMOS technologies. The modified control circuit can pass the proper voltages, required for Write/Read operations, across the nanodevice to turn it ON and OFF with 56% reduction in power dissipation. Area analysis shows that it is possible to fabricate CMOL Micro & Nano Letters, 2008, Vol. 3, No. 3, pp

7 logic and memory cells on a single chip. Nanodevices with switching voltage levels,1.3 V (for Write operation) are needed to make the proposed memory array design compatible with CMOS 45 nm, 32 nm and 22 nm technology nodes for successful hybrid integration of CMOS and molecular device technologies. 8 Acknowledgment This work was partially supported by Natural Sciences and Engineering Research Council of Canada (NSERC). 9 References [1] HANSON G.W.: Fundamentals of nanoelectronics, (Pearson Prentice-Hall, 2007), pp [2] FOLLING S., TUREL O., LIKHAREV K.: Single-electron latching switches as nanoscale synapses. Int. Joint Conf. on Neural Networks (IJCNN 01) Proc., 2001, vol. 1, pp [3] HEATH J.R., KUEKES J.G., SNIDER G.S., WILLIAMS R.S.: A defecttolerant computer architecture: opportunities for nanotechnology, Nat. Mater., 2005, 4, (2), pp [4] LIKHAREV K.: Electronics below 10 nm, Science, 1998, 280, pp [5] LIKHAREV K., STRUKOV D.: CMOL:devices,circuits,and architectures in Introducing molecular electronics (Springers, 2006), pp [6] STRUKOV D.B., LIKHAREV K.K.: A reconfigurable architecture for hybrid CMOS/nanodevice circuits. Int. Symp. Field Programmable Gate Arrays, Monterey, CA, USA, 2006, pp [7] DEHON A., LIKHAREV K.K.: HybridCMOS/nanoelectronic digital circuits: devices, architectures, and design automation, IEEE/ACM Int. Conf. Comput. Aided Des., 2005, 6, (10), pp [8] STRUKOV D.B., LIKHAREV K.K.: CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices, Nanotechnology, 2005, 16, pp [9] STRUKOV D.B., LIKHAREV K.K.: Defect-tolerant architectures for nanoelectronic crossbar memories, J. Nanosci. Nanotechnol., 2007, 7, (1), pp [10] LORTSCHER E., TOUR J.M., CISZEK J.W., RIEL H.: A singlemolecule switch and memory element, J. Phys. Conf. Series, 2007, 61, pp [11] LI C., FAN W., LEI B., ET AL.: Multilevel memory based on molecular devices, Appl. Phys. Lett., 2004, 84, (11), pp [12] LI C., LEI B., FAN W., ZHANG D.: Molecular memory based on nanowire-molecular wire heterostructures, J. Nanosci. Nanotechnol., 2007, 7, pp [13] LÖRTSCHER E., CISZEK J.W., TOUR J.M., RIEL H.: Reversible and controllable switching of a single-molecule junction, Small, 2006, 2, (8 9), pp [14] STRUKOV D.B., LIKHAREV K.K.: Prospects for terabit-scale nanoelectronic memories, Nanotechnology, 2005, 16, pp [15] Berkeley predictive technology model files for future transistor and interconnect technologies: asu.edu/ ptm/ [16] International Technology Roadmap for Semiconductors (ITRS): Available online at public.itrs.net/, 2006 [17] WESTE H.E., HARRIS D.: CMOS VLSI design: a circuit and systems perspective (Pearson Education, 2005), pp [18] DONG C., WANG W., HARUEHANROENGRA S.: Efficient logic architectures for CMOL nanoelectronic circuits, Micro Nano Lett., 2007, 1, pp Micro & Nano Letters, 2008, Vol. 3, No. 3, pp