THE INTEGRATION of nanodevices with complementary

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1 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 3, MAY Efficient CMOL Gate Designs for Cryptography Applications Z. Abid, Member, IEEE, A. Alma aitah, Student Member, IEEE, M.Barua, Student Member, IEEE, and W. Wang, Member, IEEE Abstract This paper introduces new hybrid complementary metal oxide semiconductor (CMOS)-nano (CMOL) circuits for efficient implementation of cryptographic algorithms. The novelty of this study is to utilize two types of nanojunction devices with CMOS to build the crypto IC. In particular, efficient XOR gate with resistive junctions and XOR/AND gates with diode-like junctions are develop to be used as building blocks of the corresponding modules of the Advanced Encryption Standard (AES) crypto IC. They allow a reduction of 79%, 43%, and 53% in power dissipation, area, and time delay compared to the existing CMOL implementation of AES system. When compared to field-programmable nanowire interconnect (FPNI) design of AES, a 56% increase in power dissipation was recorded in order to achieve a 92% and 15% reduction in area and time delay. This proposed circuit study also leverages the recent fabrication results, which is a feasible CMOS-nano hybrid solution for future crypto IC development. Index Terms Advanced encryption standard (AES), CMOSmolecular nanoelectronics (CMOL), hybrid complementary metal oxide semiconductor (CMOS), molecular electronics, nanotechnology. I. INTRODUCTION THE INTEGRATION of nanodevices with complementary metal oxide semiconductor (CMOS) devices [1] [8] might open new opportunities to build future ICs by offering an extremely high-density chips and defect-tolerant operations. Compared with other CMOS-nano hybrid systems, CMOL [2] [7] is a promising technology with three main key properties: 1) the uniformity of the cells; 2) the programmability and reconfigurability of the nanodevices; and 3) the flexibility to allow unprecise alignment of the top two nanowire layers relative to the CMOS stack. Such properties may allow CMOL to overcome the expected obstacles of semiconductor electronics beyond the 22-nm CMOS technology node [9]. One interesting application of the CMOL is to build future cryptography systems such as Advanced Encryption Standard (AES) that uses mostly XOR and AND gates [10] [13]. It is worth noting that the proposed CMOL cryptography system has Manuscript received July 14, 2008; revised October 10, 2008 and December 3, First published January 13, 2009; current version published May 6, This work was supported in part by the Natural Sciences and Engineering Research Council (NSERC) Canada. The review of this paper was arranged by Associate Editor K. K. Likharev. Z. Abid, A. Alma aitah, and M. Barua are with the Electrical and Computer Engineering (ECE) Department, University of Western Ontario, London, ON N6A5B9, Canada ( zeabid@eng.uwo.ca; aalmaait@uwo.ca; mbarua@uwo.ca). W. Wang is with the College of Nanoscale Science and Engineering, University at Albany, Albany, NY USA ( wwang@uamail.albany.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TNANO the reconfigurability feature due to the reconfigurable nature of the CMOL. This will allow the adaptability of the crypto processor (e.g., the AES in this paper) for different key and data lengths depending on the required performance-security tradeoffs. This reconfigurability is also critical for defect tolerance whose importance is expected to increase for nanoscale CMOS, and especially for CMOL structures. Recent results [13] show that CMOL provides considerable improvement over CMOS architecture even with a 20% defect rate, demonstrating the efficiency of CMOL-like structures in cryptography systems. However, the existing CMOL cells are based on inverter and OR/NOR gates, which are not efficient to implement XOR and AND gates. In order to tailor the CMOL structure for cryptography applications, it is important to develop XOR/AND gate-based CMOL cells. In this paper, we investigate the CMOL design of the XOR and AND gates. We will first review the existing CMOL cell designs. Then, we will introduce our CMOL XOR/AND gates designs and their use to implement AES systems. II. EXISTING CMOL DESIGNS FOR AES APPLICATIONS The CMOL structure integrates a conventional MOSFET transistor (CMOS) stack and a nanowire crossbar, with junction nanodevices (switches) formed between the nanowires at every cross point. These nanodevices are generally resistive junctions with hysteretic switching behaviors. They are reprogrammable and can be reconfigured to be either turned-off or turned-on. Depending on the materials, some devices will also have hysteretic diode-like switching behavior similar to one resistor in series with one diode. The original CMOL structure considers junction nanodevices with diode behaviors, which can be used as a memory element or part of the logic gate for field-programmable gate array (FPGA) applications. A modified version of CMOL, namely field-programmable nanowire interconnect (FPNI), utilizes the resistor junctions to improve the interconnects of an FPGA. The basic cell of CMOL is an inverter cell (I-cell) and that of the FPNI is an NAND/NOR gate cell. A. CMOL I-Cell and FPNI NAND Cell Designs A CMOL I-cell consists of an inverter and two pass transistors connected to two pins (with different heights) serving as the cell input and output [Fig. 1(a)] [5]. The CMOS row signals are used to program the nanodevices through pass transistors that are controlled by the columns signals. The CMOL wired logic [Fig. 1(b)] depends on the voltage divider between the junction switch (modeled as a resistor R ON ) and the pass X/$ IEEE

2 316 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 3, MAY 2009 Fig. 2. AES block diagram with the required gates in each of the three modules. The percentage numbers (outside the boxes) reflect the size of each module relative to the total design. Fig. 1. (a) Schematic of the CMOL inverter cell (I-cell) (the green dots are the nanodevices; the red/blue dots are the pins) [5]. (b) Equivalent circuit of the CMOL wired-or/nor gates. (c) FPNI NAND, buffers, and flip-flop cells. transistor (modeled as a resistor R PASS ) in order to provide a suitable voltage level to the input of the inverter [4] [7]. The performance (voltage level) degradation due to the wired logic (diode resistor logic family) is an issue that needs to be addressed in CMOL I-cell designs. It is required to restore the signal through an inverter with the condition that the degraded input signal is not ambiguous. Besides providing a dc path for the wired-logic gates, the pass transistor plays a major role of passing the right voltage during the programming phase of the nanojunction switches. Fig. 1(c) shows the NAND/buffers/flip-flop cells in FPNI. The NAND or flip-flop cells require multiple individual cells to accommodate large logic gates. Note that in FPNI, the nanowire crossbars are fabricated using lithography on top of CMOS pins, with same heights, allowing an easier fabrication process at the CMOS level. However, device density will be significantly reduced compared to the original CMOL. Also, since the nanodevices are resistor junctions, they can only be used as programmable interconnects, but not in logic gates. B. CMOL AES Designs AES is an iterative algorithm operating on 4 4 array of bytes (called the state), allowing only the data length to be 128 bits while conserving the property of supporting three different cipher key lengths (128, 192, and 256 bits) [14]. AES can be divided into four basic operation blocks: the SubByte transformation, the ShiftRow transformation, the MixColumn transformation, and AddRoundKey. The different transformations operate on the state and produce intermediate results with the same size as the input state. The applications of CMOL I-cells or FPNI NAND cells will significantly improve the AES implementation, especially in terms of area/density. Hardware implementation of AES mainly consists of SubBytes, MixColumns, and Key Expansion modules [14]. As shown in Fig. 2, all these modules are mainly based on AND and XOR gates. By reconfiguring CMOL I-cells or FPNI NAND cells to AND/XOR gates, the performance along with the interconnects of these modules will be improved. Furthermore, since CMOL I-cell can utilize the nanodevices as a part of the logic gates, the CMOL implementations of the AND/XOR gates are also improved [13]. Note that FPNI uses the nanodevices to improve the interconnects of these modules only while its XOR/AND gates have no improvement over the CMOS implementations of these gates. III. PROPOSED XOR/AND CELLS AND THEIR APPLICATION IN CRYPTOGRAPHY The focus of this paper is to develop novel XOR/AND CMOL designs that can efficiently implement cryptography systems such as AES. First, the novel XOR cell is introduced. The resistor junction nanodevices can be integrated on top of these XOR cells to establish the MixColumns module. Thus, the nanodevices are only used to provide the interconnects with programmable capabilities. For the SubBytes and Key Expansion modules, diode junctions are used on top of the XOR gates to form AND gates, providing XOR/AND cells. By depositing different junction materials to the three arrays of XOR gates during the fabrication process, we can implement the three modules with different junctions. A. Proposed XOR Cell for MixColumns Module The proposed design combines CMOS inverters and transmission gates to build the XOR gate using two cells (Fig. 3). The input pins of the two cells are the two inputs for the XOR gate, and the output of the right-hand cell is the output of the XOR gate, as shown in Fig. 3(b). The output pin of the left-hand cell is left floating for easier interconnect rerouting. However, it is

3 ABID et al.: EFFICIENT CMOL GATE DESIGNS FOR CRYPTOGRAPHY APPLICATIONS 317 Fig. 3. (a) Proposed XOR gate cell design. (b) Array structure based on the proposed XOR gate cell. (c) Equivalent circuit with the junction nanoswitch being a resister junction (RM) instead of a diode-like junction (DM). R w and C w represent the nanowires. possible to connect both output pins together to give more flexibility to drive other XOR gates at the expense of fixing the routing of the related nanowires. In addition to the (four) pass transistors for the programming purpose, a total of ten transistors are required for this XOR cells, leading to a larger area (equivalent to about three I-cells). Note that the inverters 1 and 2 [Fig. 3(a)] are specifically included to buffer the weak input signals. The equivalent circuit of the proposed XOR gate isshown infig. 3(c). The transistors need to be sized to adjust the voltage levels and allow the XOR gate to operate correctly. In previous CMOL I-cell designs, the voltage level at the input terminal of the inverter is a fraction of 0.3 V (V dd =0.3 V was adopted). The reason is that a voltage divider is used between R ON of the nanodevice and R PASS of the pass transistors [Fig. 1(b)]. This will compromise the operation robustness of the CMOL I-cell. For the proposed XOR cell, we adjust V dd to 1 V in accordance with the International Technology Roadmap for Semiconductors (ITRS) road map for 45-nm (or lower) CMOS technology node. The transistors of the XOR cell are resized to correctly recognize the voltage levels at its inputs from the previous non-xor gates. The first two inverters (1 and 2) in Fig. 3(a) will be sized as the inverter in the I-cell (i.e., W =10λ for NMOS, W =4λ for PMOS) in order to restore weak logic 1 input signal from previous wired-logic gates. The third inverter will receive the strong logic levels from the first inverter, and consequently, its sizing is the same as in a typical CMOS inverter (i.e., W =4λ for NMOS, W =8λ for PMOS). The sizing of the transmission gates is not as critical and does not affect the proper operation of the XOR. However, the width of the NMOS of the transmission gate #1 and the PMOS of the transmission gate #2 are wider (W =6λ) in order to overcome the weak controlling signal at their gates. The proposed XOR gate cell and the resistive junctions (RM) are combined to implement the MixColumns module, as shown in Fig. 4. The gray cells are spare ones to replace any defective XOR cells [Fig. 4(b)]. The floating output pins of some used cells are also spares that allow more flexible rerouting around defective cells and nanowires. B. Proposed XOR/AND Cells for SubBytes and Key Expansion Modules The AND gate in the XOR/AND cells is implemented using the diode-like junction nanodevices similar to the OR/NOR gates in a CMOL I-cell. The difference is that the AND gate [Fig. 5(a)] includes a new reference voltage (V mm =0.65 V) instead of the ground, and the diodes are of the opposite direction. Thus, only when the two inputs are both logic 1, the diodes are OFF and the output becomes 1. Note that the output of the AND gate is weak (Table I) and requires a skewed inverter to restore the logic levels. An AND gate generates a degraded output, but if followed by an XOR, with its intrinsic inverters, the signal can be restored without using external inverters. XOR and AND gates are the main components needed to build SubBytes (98%) and Key Expansion modules (66%), in addition to inverters and NAND gates, as shown in Fig. 3. Thus, the proposed XOR/AND design will be used as the building block for these two modules. Fig. 6 shows a portion of the SubBytes logic gate-level design and its CMOL implementation, including the XOR/AND gates. The Key Expansion

4 318 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 3, MAY 2009 Fig. 4. (a) Portion of the AES MixColumns module. A, B, X, and Y are input bytes, and M is the output byte. (b) Proposed CMOL structure of this portion of the AES MixColumn module. TABLE I WEAKVOLTAGELEVELS AT THE OUTPUT OF THE ANDGATE (SEEFIG. 5)AND THE NEED FOR A SKEWED INVERTER TO RESTORE THE LOGIC LEVELS only), and easier fabrication and configuration, but at the cost of a larger power dissipation. Fig. 5. Proposed AND gate based on nanojunction (diode-like) devices and its equivalent circuit. R w and C w represent the nanowires. logic needs about 33% of its gate as NAND gates. This can be implemented by an AND gate followed by one XOR used as inverter (one of its two inputs is connected to logic 1 ) in order to preserve the suggested array structure uniformity (XOR cells IV. SIMULATION RESULTS The proposed circuits can efficiently implement the three modules of the AES. Note that the MixColumns module is based on resistive junctions, while the Key Expansion and Sub- Bytes modules utilize diode junctions. In order to evaluate the efficiency of the proposed design, HSPICE Simulations, based on ITRS projected values of CMOS 45-nm technology, were

5 ABID et al.: EFFICIENT CMOL GATE DESIGNS FOR CRYPTOGRAPHY APPLICATIONS 319 Fig. 6. (a) Portion of the SubByte module. (b) Proposed CMOL array implementation, using XOR cells, of the five gates shown in (a). TABLE II PARAMETERS OF THE NANOWIRES, THE JUNCTION SWITCH, AND THE PASS TRANSISTORS USEDINTHECIRCUIT SIMULATION Fig. 7. Average power consumption and time delay of the XOR-only and the AND/XOR gates in CMOL I-cell [4], FPNI [8], and the proposed structure. TABLE III AREA AND THE NUMBER OF NANOJUNCTIONS OF THE XOR GATE (FOR MIXCOLUMN) AND XOR/AND GATES (FOR SUBBYTES MODULE) IMPLEMENTATIONS conducted. The main parameters (Table II) used in the simulations of the different designs are from previous simulation work [4], [8]. Fig. 7 shows the power and time-delay simulation results of the proposed XOR and XOR/AND gates along with those of previous designs [4], [8]. The power dissipation and time delay are based on the voltage supply of V DD =1Vinstead of 0.3 V [3] [7], and a threshold voltage of 0.3 V for the CMOS transistors [15]. Table III shows the area and number of cells comparison for the two different scenarios in CMOL I-cell, FPNI, and the proposed XOR structure. The variable A 0 is the area of the CMOL I-cell, which is 180 nm 180 nm for 45-nm CMOS technology node, assuming that β =4. The proposed XOR cell has a larger number of transistors, and consequently, its area increase by 56.2% relative to the I-cell that was assumed, and as a result, its β value is larger (β =5). A physical layout was conducted to confirm that such assumption was acceptable. The pass transistors are included in the area performance estimation of all modules. They are also considered as part of the equivalent circuits for the AND/XOR gates of the SubBytes and Key Expansion modules (see Fig. 5). However, the pass transistors are not included in the MixColumns module simulations since they are turned off during normal operation and are used only during the programming phase of the RM junctions [see Fig. 3(c)]. For the XOR gate, the proposed design achieves 37%, 45%, and 87% improvement over CMOL I-cell in terms of area 1, time delay, and power dissipation. Compared with FPNI, the improvements are 75%, 32%, and 21% for area, time delay, and power. For AND/XOR gates, the proposed design can achieve 61%, 56%, and 72% improvement over CMOL I-cell in terms of area, time delay, and power dissipation. Compared with FPNI, the improvements are 88% and 13% for area and time delay at the cost of 43% increase in power. Since the three modules of AES mostly consists of XOR and XOR/AND gates, at least 43%, 53%, and 79% improvements for area, time delay, and power can be expected by using the proposed components for a complete AES system compared with CMOL I-cells 1. However, when compared to FPNI design, there is a significant reduction in area 92% and time delay 15% at the expense of a 56% increase in power dissipation. This is partially due to the use of XOR as inverters in the proposed design to implement NAND, and inverter gates in SubBytes and Key Expansion modules of AES, causing larger power dissipation, 1 Even though there is a floating pin in the XOR cell [Fig. 3(a)] dedicated for rerouting, some buffer cells may be necessary for a complete placement and routing of each of the three modules of the AES cryptosystem (see Fig. 4 for a part of the MixColumns module). Therefore, the current area estimation is a lower bound of the actual area calculation. Since the same estimation is applied to the three designs, the cell comparison in Table III indicates the actual area comparison results.

6 320 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 3, MAY 2009 but keeping the uniformity of the XOR gate cells of the CMOL array. The power density of the proposed AES cryptosystem is expected to be higher than if implemented based on FPNI, but lower than I-cell design. This is due to FPNI s CMOS-only gates [8] requiring more than 4X area of our proposed design, but with similar power consumption. Compared to I-cell design, the proposed method reduces both area and power consumption due to the use of dedicated XOR/AND gates instead of OR/NOR gates [4], as shown in Table III. Since the power reduction is more significant than the area saving, the proposed implementation shows lower power density than the corresponding I-cell design. The exact estimation of the power density depends on the area of the AES system that can be calculated based on the defect tolerance of the chip along with the assumed defect density of the fabrication process. High-performance chip, as it is for our design, shows high power density that can be reduced by lowering the supply voltage, increase the R ON (for the diode resistor logic), increase the area of the cells, and increase the transistors threshold voltage with the cost of compromising the speed and density of the chip. The superior performance of the proposed designs indicates that they can be used to establish efficient CMOL crypto IC. In order to simplify the nanodevice fabrication, the proposed design can be based on diode-like junctions only, enabling the use of AND gates. The only affected module is the MixColumn that constitutes 15% of the AES cryptosystems. Compared with the XOR-based design, this AND-based MixColumn design will degrade the power and speed performance without affecting the area performance. So, it is possible to keep the homogeneity of the CMOL structure at a small performance penalty. V. CONCLUSION In this paper, new CMOL XOR circuits are developed to achieve efficient implementation of the cryptographic algorithms. By utilizing both resistive and diode-like junction nanodevices, these circuits provide a significant reduction of time delay and chip area, compared with the previous designs. The proposed circuits stem from the recent development in fabricating different types of nanodevices with CMOS, which is a significant contribution to the CMOS-nano system design. Furthermore, this circuit analysis and design work will provide guidelines to the fabrication work. The integration of circuit studies and experimental work will setup a strong foundation to push CMOS-nano hybrid system into reality. REFERENCES [1] M. R. Stan, P. D. Franzon, S. C. Goldstein, J. C. Lach, and M. M. Ziegler, Molecular electronics: From devices and interconnect to circuits and architecture, Proc. IEEE, vol. 91, no. 11, pp , Nov [2] K. K. Likharev and D. Strukov, CMOL: Devices, circuits, and architectures, in Introduction to Molecular Electronics. G. Cuniberti et al., Eds. Berlin, Germany: Springer-Verlag, 2005, pp [3] D. B. Strukov and K. K. Likharev, A reconfigurable architecture for hybrid CMOS/nanodevice circuits, in Proc. FPGA 2006, Feb., pp [4] D. B. Strukov and K. K. Likharev, CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices, Nanotechnology, vol. 16, pp , [5] K. K. Likharev, A. Mayr, I. Muckra, and O. Turel, CrossNets: Highperformance neuromorphic architectures for CMOL circuits, Ann. NY Acad. Sci., vol. 1006, pp , [6] D. B. Strukov and K. K. Likharev, CMOL FPGA circuits, in Proc. WorldComp 2006/CDES 2006, pp [7] C. Dong, W. Wang, and S. Haruehanroengra, Efficient logic architectures for CMOL nanoelectronic circuits, IEE (ICT) Micro Nano Lett., vol.1, no. 2, pp , [8] G. S. Snider and R. S. Williams, Nano/CMOS architectures using a fieldprogrammable nanowire interconnect, Nanotechnology, vol. 18, pp , [9] International Technology Roadmap for Semiconductors (ITRS). (2006) [Online]. Available: public.itrs.net/ [10] X. Zhang and K. K. Parhi, High speed VLSI architectures for the AES algorithm, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 9, pp , Sep [11] N. Sklavos and O. Koufopavlou, Architectures and VLSI implementation of the AES-proposal Rijndael, IEEE Trans. Comput., vol. 51, no. 12, pp , Dec [12] S. Morioka and A. Satoh, An optimized S-box circuit architecture for low power AES design, in Proc. CHES, 2002, pp [13] M. Masoumi, F. Raissi, M. Ahmadian, and P. Keshavarzi, Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal oxide semiconductor molecular circuits, Nanotechnology, vol. 17, pp , [14] J. Daemen and V. Rijmen, The Design of Rijndael: AES The Advanced Encryption Standard. Berlin, Germany/Heidelberg, Germany: Springer-Verlag, 2002, ch. 4. [15] BSIM4 Predictive Transistor Models (PTM). (2008). [Online]. Available: Z. Abid (M 93) received the B.Sc. degree from the University of Setif, Setif, Algeria, in 1983, and the M.Sc. and Ph.D. degrees from the University of Minnesota, Minneapolis, in 1987 and 1991, respectively. He was a Research Associate and Lecturer at the University of Minnesota during He then was with the National Research Council (NRC), Ottawa, Canada, where he worked the fabrication, design, and characterization of high-frequency III V heterostructure bipolar transistors (HBTs). He joined Nortel networks, Ottawa, in 1995, where he worked on GaAs HBTs processing for high-frequency ICs. He was an Assistant Professor at the Department of Electrical Engineering, King Saud University, Riyadh, Saudi Arabia. In September 2002, he joined the Department of Electrical and Computer Engineering, University of Western Ontario, London, Canada. He is the author or coauthor of more than 50 papers in journals and conferences proceedings. His current research interests include hybrid CMOS digital circuits, nanoscale memory devices, 3-D ICs, defect-tolerant and low-power very largescale integration (VLSI) circuits, and resistive RAM (RRAM)-based switches and field-programmable gate arrays (FPGAs). A. Alma aitah (S 09) received the B.Sc. degree in computer engineering from Mu tah University, Al-Karak, Jordan, in 2005, and the M.Sc. degree in electrical and computer engineering from the University of Western Ontario, London, Canada, in He is currently working toward the Ph.D. degree in computer science at Queen s University, Kingston, ON, Canada and is associated with both the Telecommunication Research Laboratory (TRL) and the Satellite and Mobile Communication Laboratory. From 2005 to 2006, he was the Network Management Center (NMC) Administrator with Zain Telecommunication Network, Amman, Jordan. His current research interests include emerging devices and programmable structures for power-efficient and secure radio frequency identification (RFID) systems and wireless sensor networks.

7 ABID et al.: EFFICIENT CMOL GATE DESIGNS FOR CRYPTOGRAPHY APPLICATIONS 321 M. Barua (S 09) received the B.Sc. degree in computer science and engineering from the University of Asia Pacific, Dhaka, Bangladesh, in 2000, and the M.Sc. degree in electrical and computer engineering from the University of Western Ontario, London, Canada in He is now working toward the Ph.D. degree in electrical and computer engineering at Queen s University, Kingston, ON, Canada. From 2000 to 2005, he was a Lecturer with the University of Asia Pacific (UAP), Bangladesh. He received the Ontario Graduate Scholarship (OGS) in 2007 and the R.S McLaughlin Fellowship in 2008, and the Natural Sciences and Engineering Research Council of Canada (NSERC) (CGS-D) from 2009 to He is currently with the Queen s Satellite and Mobile Communication Laboratory, Kingston, as a Project Coordinator. His current research interests include nanoelectronics, communication security, protocol efficiency, and reconfigurable architecture design of wireless sensor networks. W. Wang (S 99-M 02) received the Ph.D. degree in electrical and computer engineering from Concordia University, Montreal, QC, Canada, in From 2002 to 2004, he was an Assistant Professor in the Department of Electrical and Computer Engineering, the University of Western Ontario, London, ON, Canada. From 2004 to 2007, he was an Assistant Professor in the Department of Electrical and Computer Engineering, Indiana University-Purdue University Indianapolis (IUPUI). Since 2007, he has been a Senior Research Scientist and Assistant Professor in the College of Nanoscale Science and Engineering, University of Albany, Albany, NY. He developed several nanoelectronics simulation tools at NanoHub. He is the holder of three US patents. He is the author or couauthor of more than 90 journal and conference publications. His current research interests include nanoelectronics, 3-D IC, CMOS-nano hybrid circuit, emerging memories and devices, and carbon nanotube and graphene. Dr. Wang is a member of the IEEE Nano and Giga Committee and the VLSI System Design Committee. He received the Canadian Foundation of Innovation Award (nanoelectronics) in 2004, the Indiana Purdue University Research Initiative Award (nanoelectronics) in 2005, the IBM Faculty Award in 2008, and coauthored the Best Paper Award from IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) Conference in He is also an EditoroftheJournal of Computer Science and Technology and the Journal of Computers.