Integrated Circuit Technology (Course Code: EE662) Lecture 1: Introduction

Transcription

1 Indian Institute of Technology Jodhpur, Year Integrated Circuit Technology (Course Code: EE662) Lecture 1: Introduction Course Instructor: Shree Prakash Tiwari, Ph.D. Office: 3106, Phone: Webpage: Course related documents will be uploaded on Note: Note: The information provided in the slides are taken mainly form text of Silicon VLSI Technology (Plummer, Deal, and Griffin) and Design(Jan M. Rabaey), and from other resources from internet; for teaching/academic use only 1 What is this course all about? Course Objectives: Understanding of the fabrication methods and unit processes for device and circuit fabrication and issues in current ULSI Unit Processes Emerging CMOS technologies Learning the scientific principles associated with the technologies used in VLSI fabrication. Exposure to the processing for newer technologies Outcome: Understanding of fabrication processes and technology associated with it 1

2 Books Text Books: James D Plummer, Michael D Deal, Peter B. Griffin, Silicon VLSI Technology Fundamentals, Practice And Modelling, Pearson (2009) S.M.Sze, VLSI Technology, Tata McGraw Hill, Stephen Campbell, The Science and Engineering of Microelectronics Fabrication, Oxford University Press, Evaluation Theory Midterm Exam 1 20% Midterm Exam 2 20% Final Exam 35% Lab/Assignment 25% 4 2

3 ENIAC The first electronic computer (1946) Dawn of the Transistor Age 1947: Bardeen and Brattain create point-contact transistor w/two PN junctions. Gain = : Shockley develops junction transistor which can be manufactured in quantity. 3

4 Introduction Co recipient of Nobel prize in physics in 2000 First Point contact Transistor (1947, Bell Labs) with Germanium semiconductor, and two gold contacts separated by 50 micron. Bardeen, Brattain, and Shockley Bell Laboratories, The Nobel prize was given in First IC, Developed independently by J. Kilby (Texas Instruments) and R. Noyce, J. Hoerni (Fairchild Semiconductor), Evolution of Electronic Devices 8 4

5 1959: Planar Technology Developed at Fairchild Semiconductor Planar Technology (Jean Hoerni): base region is diffused into collector (substrate) and emitter region into the base Integrated Wiring (Robert Noyce): By covering the planar transistor with an oxide, a layer of aluminum can be used on top to wire the device(s) : First Commercial Planar ICs Based on the planar process by Hoerni and Noyce, Fairchild developed family of logic chips called resistors transistor logic(rtl) Example shown is flip flop with 4 bipolar transistors and five resistors it 10 5

6 Practice Makes Perfect 1961: TI and Fairchild introduced first logic IC (cost ~ $50 in quantity!). This is a dual flip flop with 4 transistors. 1963: Densities and yields improve. This circuit has four flip flops. The First Integrated Circuits Bipolar logic 1960 s ECL 3-input Gate Motorola Digital Integrated Circuits, 2 nd Ed., Rabaey. 6

7 Practice Makes Perfect 1967: Fairchild markets the first semicustom chip. Transistors (organized in columns) can be easily rewired to create different circuits. Circuit has ~150 logic gates. 1968: Noyce and Moore leave Fairchild to form Intel. By 1971 Intel had 500 employees; By 2004, 80,000 employees in 55 countries and $34.2B in sales. The Big Bang 1970: Intel starts selling a 1k bit RAM, the : Ted Hoff at Intel designed the first microprocessor. The 4004 had 4 bit busses and a clock rate of 108 KHz. It had 2300 transistors and was built in a 10 um process. 7

8 Exponential Growth 1972: 8080 introduced. Had 3,500 transistors supporting a byte wide data path. 1974: Introduction of the Had 6,000 transistors in a 6 um process. The clock rate was 2 MHz. From 4 Transistors to 300 mm Wafers Batch Fabrication 16 8

9 Intel Core 2 Microprocessor In mm 2 3 GHZ operation 65 nm CMOS technology 291 mln transistors Integrated Circuits 22 nm CMOS 18 9

10 Moore s Law In , GordonMoorenoted noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months 19 1,000,000 K Moore s Law 1 Billion Transistors!!! 100,000 10,000 1, Pentium III Pentium II Pentium Pro i486 Pentium i Projected Source: Intel Transistors on Lead Microprocessors double every 2 years 20 10

11 The Ever Shrinking Transistor Using 45 nm technology, 400 transistors fit on a red blood cell! 21 Design Hierarchy SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE D n+ Digital Integrated Circuits, 2 nd Ed., Rabaey

12 Complementary MOS Transistors (CMOS) Fabricate PMOS and NMOS devices on the same substrate to build complementary MOS (CMOS) This is solved by using a p tub diffusion to create the background for the n channel devices V DD [Adapted from Copyright 1996 UCB] A p n GND Y = A' Advantages of CMOS Very low power consumption. Rilt Rail to rail voltage. Choice of the Modular design. industry! Reliable and robust

13 Not only Conventional CMOS Tsai et al ( Yoo et al. High performance CMOS-compatible superjunction FINFETs for Sub-100V Applications (IEDM 2010) Au source electrode (30 nm) 25 nm thick organic semiconductor Au Drain electrode (30 nm) Xie et al. Breakdown Voltage Enhancement Technique for RF Process Compatible Power AlGaN/GaN HEMTs (ISPSD 2012) 3.6 nm thick AlO x (gate dielectric) Al Gate PEN substrate 1.7 nm thick HC 14 PA (SAM) S. Bisoyi et al., Organic Electronics. 15, 3173 (2014) Evolution of Electronics 13

14 Summary CMOS will be continuing for next many years Proper understanding and Training for CMOS and VLSI is required Research for new device designs and materials is necessary Exploratory work should also be encouraged for new technologies 27 For researchers. New Circuit Design Techniques Novel Device Structures Double gate MOSFETs FinFETs New materials for electronics Graphene Carbon nanotubes (CNTs) Organic semiconductors Cost reduction and large area circuits/systems Organic/Flexible/printed Electronics Along with training and manpower building, exploratory research is necessary 28 14

15 Lab assignment