The challenges of configurable hybrid Memristor-CMOS Integrated circuits fabrication

Transcription

1 The challenges of configurable hybrid Memristor-CMOS Integrated circuits fabrication 30 nm Hewlett-Packard Laboratories, Palo Alto CA Gilberto Medeiros Ribeiro 2010 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice

2 Acknowledgements: Julien Borghetti John Paul Strachan Dmitri Strukov Feng Miao Wei Yi Matthew Pickett Douglas Ohlberg Qiangfei Xia Ruth Munstermann Xuema Li Tan Ha Cuong Le Phil Kuekes Alexandre Bratkovski Greg Snider Janice Nickel Stan Williams Information and quantum Systems Lab: Photonics, CeNSE & Nanoelectronics groups Lab Director: Stan Williams

3 5 exabytes in 2002 to 280 exabytes in 2009 of online data Physics of data, Marissa Myers, Google 16X Moore s law in seven years

4 Data Storage ~170%/year Compound Annual Growth Rate Hard disks are cheap, but latency limits current applications; additionally, superparamagnetism prevents much further scaling Flash as a hard disk replacement is on course Flash edging its scaling limits DRAM roadmap ends in 2015 Need for Non-volatile, scalable memory 4

5 Non-volatile storage options F=technology node Memory Element Cell size CMOS Integration Switch Mechanism Bipolar /Unipolar Scaling Ultimate Scaling Limit Setreset Times Maturity Metal Oxide * 4F 2 Excellent E-field Bipolar Good Conducting channel size (5nm) Good Lab-tofab PCM * 4F 2 Demonstrated Temperature Unipolar Fair Stable nanocrystal size (~10nm) Good First products Flash *4F 2 Excellent E-field N/A Fair Capacitor size Fair Product FeRAM *4F 2 Demonstrated E-field Bipolar Poor Domain size (20nm) Good Product MRAM *4F 2 Poor (Fe) B-field Bipolar Poor Domain size (10nm) Good Specialty product 5

6 Outline History, definitions: Memristor, the 4 th passive element TiO 2 : Materials Science Engineering TiO 2 based memristors: Implementation; electroforming Synchrotron investigations From Physics to engineering: IC design Fabrication Summary 6

7 Outline History, definitions: Memristor, the 4 th passive element TiO 2 : Materials Science Engineering TiO 2 based memristors: Implementation; electroforming Synchrotron investigations From Physics to engineering: IC design Fabrication Summary 7

8 The memristor as the fourth element RESISTOR v = R i L. O. Chua, IEEE Trans. Circuit Theory 18, 507 (1971) CAPACITOR dq = C dv INDUCTOR dφ = L di MEMRISTOR dφ = M dq rigorous definition v( t) R[ w, i( t)] i( t) Quasi-static conduction eq.- R depends on state variable w dw( t) dt f [ w, i( t)] Dynamical equation: Evolution of state in time 8

9 What makes the memristor fundamental? Current vs. Sinusoidal Voltage Current Current Current Voltage Resistor Time Capacitor dv = R di dq = C dv Inductor Memristor dφ = L di dφ = M dq Voltage Voltage 9

10 4 properties of memristive systems in 3 sweeps: a dynamical device 134 Memristive Properties Continuous states Zero-crossing Frequency dependent Bias dependent 2 10

11 Semi-empirical model: static snapshot Pickett et al., J. App. Phys. 106, Equivalent circuit consisting of: series resistor Rs; tunneling barrier of thickness w; Simmons equations were utilized to infer w 11

12 Semi-empirical model: dynamical evolution Pickett et al., J. App. Phys. 106,

13 Outline History, definitions: Memristor, the 4 th passive element TiO 2 : Materials Science Engineering TiO 2 based memristors: Implementation; electroforming Synchrotron investigations From Physics to engineering: IC design Fabrication Summary 13

14 TiO 2 14

15 TiO 2 rutile TiO2 (110) Splitting water Paul Kent/ORNL 3.0/3.2 ev semiconductor dielectric ε ~ 80, bi-refringent pigment, photocatalyst, O 2 sensors TiO 2 : 1x Ti x O 2- rutile TiO2 anatase TiO2

16 Ti-O phase diagram: Many sub-oxides Easy to be partially reduced 16

17 Au Au Ag Pt Ni W Ti Reduction capability increasing [Vo] creation increasing TiO 2-x Ni W Ti 3 O 5 Ti Pt

18 Outline History, definitions: Memristor, the 4 th passive element TiO 2 : Materials Science Engineering TiO 2 based memristors: Implementation; electroforming Synchrotron investigations From Physics to engineering: IC design Fabrication Summary 18

19 For device operation, an electroforming cycle is necessary for most devices Pt 33nm TiO 2 Pt 19

20 Transmission Geometry studies For transmission techniques, devices fabricated on thin windows of Si 3 N 4 Side view Pt TiO 2 Pt Si 3 N 4 Si Si 3 N 4 Membrane Top view μm x 1.5μm junction

21 Scanning Transmission X-ray Microscopy Contrast observed within the Ti L-edge 450 ev 200 nm 460 ev 200 nm 475 ev nm

22 Identification through local electron diffraction+spectroscopy: Feature is Ti 4 O 7, a reduced form of TiO 2 which is highly conductive and act as a reservoir for O vacancies: 22 Forming can be eliminated by choosing the right layer sequence Rutile, [100] Ti 4 O 7, [100] J.P. Strachan et al., Adv. Mat. (2010)

23 Outline History, definitions: Memristor, the 4 th passive element TiO 2 : Materials Science Engineering TiO 2 based memristors: Implementation; electroforming Synchrotron investigations From Physics to engineering: IC design Fabrication Summary 23

24 Current (A) Simple Spice Model for Circuit Verification State of the art model at time of design, a more detailed model exists now. Bench Data provided by HPL Junction IV Characteristics Ion Ioff , E , E Voltage (V) Simplified Model Ik sinh *Vk State Alpha Beta Avg of RMS error OFF 2.29E E-08 ON 1.73E E-08 Actual device model used for CMOS verification 24

25 Hard Coded Die Configuration in start A B half-adder Q D FF Time S C out in out LSB time 0 MSBB In order to mitigate design risk, and speed up test development, CMOS configured (NIL not needed) was provided. 1 1 Q

26 SNIC Architecture 26

27 CMOS Integration Challenges Challenges: Unstable process for nanowires Design needed to enable process development Driver circuitry for a dynamical load Different operating voltages Implication: Design had to provide a flexible interface for fab and lab quality imprint tooling Larger than necessary alignment tree Risks Unknown Fab-Lab integration challenges 27

28 Quartz NIL Molds Bottom Electrode Top Electrode Holey Pad Structure Master mold patterned by EBL. Daughter molds duplicated on QZ using NIL. Nanowires:100 nm HP. Feature height: 60 nm. Pad size: 10 m by 15 m. 28

29 CMOS Substrate 3 metal layer CMOS circuits, [0, 3.3V] operation. Chip finished with TEOS and CMP. Fabricated with 0.5 m technology at HP Corvallis fab in Oregon 29

30 Integrated Hybrid Circuits (c) 100 nm 12 nm Pt 36 nm TiO2 9 nm Pt 2 nm Ti 30

31 Wiring of Logic Gates Using Memristors 31

32 Logic Functions Successfully Implemented NOT gate A C AND gate A B C 1 OR gate A B C 1 32 Reading voltage: 1.7 V. CMOS: 3.3V

33 Logic Functions Successfully Implemented NAND gate A B C 1 NOR gate A B C 1 D Flip-flop D Clk Q Q 33

34 Reconfigurability Demonstrated ON OFF INPUT INPUT OUTPUT Reading voltage: 0.5 V OUTPUT Qiangfei Xia et al, Nano Lett., 2009, 9 (10), pp

35 Outline History, definitions: Memristor, the 4 th passive element TiO 2 : Materials Science Engineering TiO 2 based memristors: Implementation; electroforming Synchrotron investigations From Physics to engineering: IC design Fabrication Summary 35

36 Summary Materials Physics Engineering chips V I mobile donors fixed acceptors Mixed conduction: electrons and ions Reconfigurable logic demo Phase identification and control 36

37 Outlook Numerous other possibilities, eg., implication logic: Borghetti et al., Nature 873, 464 (2010) pimpq (NOTp)ORq Analog properties untouched 37

38 Thank you 38