Memristive memories and photonic interconnects in the data-centric datacenter

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2 Memristive memories and photonic interconnects in the data-centric datacenter Marco Fiorentino HP Labs Information and Quantum Systems Lab 2008 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice

3 Motivation Computing landscape Data grows faster than computation Online data increased 95%/yr (Google) Storage growth 56%/yr (IDC) Moore s Law growth 40%/yr Data-centric workloads Distribute/locally transform/transmit data Diverse access patterns and locality Diverse compute requirements Shift from performance to efficiency Cost Sustainability 3

4 Data-centric datacenter (DC-DC) Data-centric datacenter Large amounts of data Scalable Lots of storage/memory/compute power Non local data large communication bandwidth Management tools for large shared data sets Programmable Low TCO Easy management Power/cooling Disaggregated servers/hybrid computing Memristive memories CeNSE Cloud computing Data mining Applications Data-centric datacenter Balance Networking Photonic interconnect Business intelligence 4 OS/Software stack/eaas

5 Photonic interconnect 5

6 HP photonic lineup Hybrid laser Active cable Optical Bus cable Silicon PIC On-chip interconnect Rx Rx Rx Rx Rx Rx Rx Rx Tx Now 1 Year 3 Years 5 Years 7 Years 10 Years Single wavelength CWDM DWDM 100pJ/bit >.1 pj/bit 6

7 Photonic Bus Ch 0 Tap 1 Tap 2 Tap 3 Tap 4 Tap 5 Tap 6 Tap 7 Tap 8 Faulty Rx Ch 1 Ch 2 Ch 3 Array of 4 HMWG 8 taps/channel < 0.07 db/cm propagation losses Pellicle beamsplitter 0.15 db/tap excess losses 10 Gbs/channel Mike Tan

8 Hybrid ring laser Di Liang & John Bowers under HP Labs Innovation Research Program Award Hybrid Si-InAlGaAs platform Wafer bonding Self-aligned process 300 µw output Up to 65 C lasing observed Single transverse mode 10 GHz 3 db BW expected Can be used for CWDM link LI curves Spectrum 8 Di Liang UCSB

9 Silicon integrated circuits 10 µm silicon ring resonators Results Charge injection 1310 nm (compatibility with Ge detectors) Q ~ 10, Ω series resistance (pads) 0.18 nm shift (thermal limit) 18 db extinction 0.6 mw 3 Gbps modulation 1.2 CW tuning Al Ni Cross section PECVD Oxide cladding Si p+ Si n+ Si BOX Al Ni Si Substrate <100> Top view Eye diagram RZ 3 Gbps Normalized intensity 9 1 ON V V 0 OFF Wavelength (nm) Zhen Peng HP labs

10 Corona Optical hub Compute Network 10 TFlop/s total compute BW 20 TB/s on-chip data BW 200 W power consumption 20 TB/s off-chip data BW 50 W power consumption Up to 20x performance improvement over electrical interconnects

11 Memristive memories 1 1

12 HP s memristors Memristor = resistor + memory Small Fast Low power CMOS-ready Current (ua) Switching I-V ON OFF 50x50 nm Pt TiO 2 TiO 2-x Pt Voltage ( V ) Electrons: (-en(x) µ n φ n (x)) = 0 Holes: (ep(x) µ p φ p (x)) = 0 Ions: - (- ed i N D (x) - en D (x) µ i φ(x)) = e N D (x)/ t Poisson: -εε 0 φ(x) = e[p(x)-n(x)+ f D (x) N D (x) - f A (x) N A ] 12 Pt TiO 2 TiO 2-x Pt V mobile donors + - I fixed acceptors electronic current Stan Williams HP labs

13 Memristors scorecard Switching voltage:1-2 Volts Data retention time: years (measured) Switching current: <20µA ON/OFF ratio (>1000:1); allows multiple bits Write/Erase/Read speed: <10ns Endurance: >10 5 cycles Write/Erase/Read energy: ~pj Density: 100 Gb/cm 2 Memory Element Density CMOS Integration Switch Mechanism Bipolar / Unipolar Power Scaling Ultimate Scaling Limit Set-reset Times Maturity Metal Oxide * 0.5F 2 Excellent E-field Bipolar Good Good Conducting channel size (5nm) Good Lab-to-fab PCM *4F 2 Demonstrate d Temperature Unipolar Poor Fair Stable nanocrystal size (~10nm) Good Prototype Flash *4F 2 Excellent E-field N/A Good Fair Capacitor size Fair Product FeRAM *4F 2 Demonstrate d E-field Bipolar Good Poor Domain size (20nm) Good Product MRAM *4F 2 Poor (Fe) B-field Bipolar Poor Poor Domain size (10nm) Good Specialty product 13 * F is the technology node feature size Gio Medeiros Ribeiro HP labs

14 NVRAM on CMOS Issues that had to be overcome: 3x3 100nm nanowire planarity alignment of fine features Crossbar junctions CMOS chip with memristive devices Connecting the CMOS layer with the nanowire crossbar junctions

15 The data-centric datacenter 15

16 New architecture Rethink the datacenter around a processor with on-chip NVRAM Modular & tunable compute/memory/datastore sockets Radically simplified cores (slow/simple) Hybrid hierarchical network (for efficiency) Electrical at low level (chip board) Photonics at high level (blade datacenter) Open question: can we go photonics all the way? Old server New server 16

17 By the numbers preliminary results Socket Dual core processor100 MHz-1 GHz 100 Gb storage 1 Gb/s Board 192 sockets 0.5 Tflop, Gb/s 1 Gb/s network 65 W Blade 4 boards Optically connected Aggregated cooling Rack 24 blades Network switch included Container 36 racks 1 Pflop, 65 PB, 325 kw Performance 2x-20x better performance/watt than standard solution Stay tuned for more from HP s Exascale Computer Lab 17

18 Conclusion Computing You think is increasingly you need photonics data-centric today New technologies like memristors and photonic interconnects are needed to face this challenge wait and see what will hit you tomorrow 18

19 The stone soup slide show Memristors Stan Williams Gio Medeiros-Ribeiro Julien Borghetti, Matthew Pickett, Warren Robinett, Duncan Stewart, John Paul Strachan, Dima Strukov, Qiangfei Xia, Jianhua Yang Photonics Ray Beausoleil Zhen Peng Mike Tan Di Liang (UCSB) David Fattal, Sagi Mathai, Paul Rosenberg, Charles Santori Architecture Partha Ranganathan Jichuan Chang David Roberts Jung-Ho Ahn, Nate Binkert, Naveen Muralimanohar, Norm Jouppi, Rob Schreiber, Dana Vanatrease Business/Vision Terry Morris Greg Astfalk Pete Hartwell (CeNSE) 19 August

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21 The memristor Ohm 1827 v Von Kleist 1745 i RESISTOR dv = R di INDUCTOR dφ = L di dφ/dt = v CAPACITOR dq = C dv dq /dt = i MEMRISTOR dφ = M dq q rigorous definition L. O. Chua, IEEE Trans. Circuit Theory 18, 507 (1971) Quasi-static conduction eq.- R depends on state variable w 1831 Faraday φ 1971 Chua Dynamical equation Evolution of state in time

22 4-D Address Space to access M crossbars! Virtual N 2 x N 2 crossbar M = N 2 /β 2 device in 1 st layer device in 2 nd layer wiring layer Xbar layer CMOS layer ~N 2 β 2 Xpoint devices per layer (out of N 4 total) N data/control lines N 2 access devices Can address any crosspoint in M crossbars with a single sparse set of vias! The CMOS pitch can be much larger than the crossbar pitch