Silicon Photonics: A Platform for Integration, Wafer Level Assembly and Packaging

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1 Silicon Photonics: A Platform for Integration, Wafer Level Assembly and Packaging M. Asghari Kotura Inc April 27

2 Contents: Who is Kotura Choice of waveguide technology Challenges and merits of Si photonics packaging Integration: High functionality and lower component count Fibre interface Stress related issues Thermal management Hybrid assembly Examples of current activities 2

3 Who is Kotura? Founded in 23: Merger of two companies A Leading Silicon Photonics Company Shipping in volume to Tier-1 customers Products deployed in live networks Over 5 patents issued / pending and license to all Bookham Si based IP. Strategy based on partnership Build competence on chip design and fabrication Be a high value, high functionality chip supplier Form partnerships for product development, fast market penetration and achieving maximum application coverage In house Si Fab, prototype packaging and low volume A&T.25um DUV Scanner, World Class Dry Etch Capability,... Sub Con manufacturing partner in China Happy to work as partner / foundry on a joint development or sub-contract basis 3

4 Si Technology: Basics Key Strengths - Manufacturability -Scalability - Volume cost curve - Process control - Potential for integration - Solid state reliability - Electronic integration - Full set of functionality Passive devices Current injection devices Detectors, VOAs etc Hybridisation capability Silicon thickness Waveguide width Si Si substrate Ridge height Oxide Material Property Refractive Index Material Type Si 3.47 Well controlled Crystal dn / dt 1.8x1-4 K -1 Key Challenges - Fibre interface - Temperature control - Stress issues on packaging Thermal Conductivity, K Tuning Temp Stability W/mK 85 pm / o C + / -.1 o C 4

5 Choice of Waveguide Technology 1 Experimental data 1 Bend Radius (mm) Bend Radius (mm) Propagation Loss (db/cm) Deep etch technology Propagation Loss (db/cm) Waveguide Dimension (um) Photonics sweet spot Kotura 1 Electronics III/V Fiber 5

6 Choice of Waveguide Technology Crosstalk (db) Propagation loss independent of Wavelength and Polarization Very low group velocity and polarization mode dispersion Very low waveguide crossing loss and X-talk Optimum core size for most optical functionalities is at 3 to 4um X-Talk H Loss XTalk_TE(.5um) XTalk_TE(1um) XTalk_TE(3um) Loss_TE(.5um) Loss_TM(.5um) Loss_TE(1um) Loss_TM(1um) Loss_TE(3um) Loss_TM(3um) H Theoretical Loss (db) Propagation Loss (db) 3um Core Waveguide Experimental TE Wavelength (nm) Group index Effective index TM TE(dB/cm) TM(dB/cm) TE TM Effect and group index Waveguide Width, W ( um) WG Thickness (um)

7 Passive Waveguide Technology Key Components Bends and Mirrors Couplers and splitters Mode transformers Wavelength Mux / Demux / selective elements Polarisation splitters, rotators and discriminators Optical / modal Filters Transmission (db) <.1dB Loss for U-bend with 25um Radius Part 1 R Part 2 Part Frequency (THz) Number of Combinations Intra-channel Crosstalk (db)

8 Current Injection Devices: VOA example 5 45 BOX n-type p-type p+ n+ Silicon Normalised phase change SOI - Carrier injection 1 mw SOI Thermal Thin BOX 4mW SOI Thermal Thick BOX 4mW Time (ms) Silica 4mW Attenuation (db) Current (ma) 1 Attenuation (db) Phase Shift (units of Pi) Extinction / db MZ switch Bar TE Bar TM Cross TE Cross TM Applied Current / ma

9 III/V Device Hybridization wirebond Laser / SOA Hybridization Shelf on which the laser is mounted Solder Metal track Vertical plinth Solder Si Metalization Commodity actives for low cost Accurate vertical alignment is achieved by removing low tolerance layers from the laser and accurate etching in Si of mounting shelf Alignment marks aim to achieve maximum lateral placement accuracy Si plated with solder and includes some simple electronics components On placement of laser local heating is applied to reflow the solder Si Waveguide Photo-diode Hybridization High Resisitivity Si for RF Lines Waveguide Mirror Horizontal taper in Si can improve lateral coupling loss due to lateral placement in-accuracies 9

10 Fiber Coupling Kotura s Patented Epi Taper technology enables: - Fiber mode matching with no compromise in device performance - Core size reduction evolution 1um to 4um core 12um core A three dimensional taper (mode expander) reduces coupling loss to <.5dB. The back reflection from such a facet is <-5dB PDL is <.5dB Wavelength and Temperature insensitive Technology offers low cost passive V- groove based fibre attach Back Reflection D Taper Vertical Fibre position (um) -65dB 1

11 Stress Management Challenges: Si is prone to stress induced index change Stress induced x & y index change This can cause polarization conversion, polarization mode dispersion and PDL A combination of stress and roughness can also cause mode conversion Strain not included Strain included Ex field Ey field ~.% TM Typically.1% TM Ex field Ey field Stress and roughness can cause mode conversion 11

12 Stress Management Benefits Stress can be used for performance correction eg on AWG array for PDF. Stress can be utilized for sensor applications Before PDF Compensation PDF (GHz) Channel After PDF Compensation 12

13 Thermal Considerations High Si dn/dt requires a high level of thermal stability High thermal conductivity of Si enables excellent temperature uniformity and effective heat removal 3 channels on 1 channel VOA Temp differential on chip, DT =.38 o C 25 Developments in Si packaging have enabled better than.1 o C thermal management even with high power and time varying thermal dissipation at chip level. Integrated temperature sensors can be fabricated into the fabric of the Si chip close to sensitive areas Resistance (Ohms) nin:.5% C -1, pip:.7% C -1 Grid Offset / pm 9 channels on Improvements made in thermal management of Si PLCs DT =.37 o C Temperature (deg C) Ambient Temperature / DegC

14 Thermal Considerations. Thermal isolation features such as deep etches and bridge structures can be fabricated to enable thermal isolation Si and InP based devices have very similar wavelength drift with temperature Thermal isolation trench 4 Wavelength Shift (nm) 3 DFB (.1) 2 DFB(.8) 1 AWG (Si) AWG (SiO2) Temperature (C)

15 Si Integrates Waveguides and Micro-Bench Capabilities Front Facet Monitor BOX p + n + Passive Fiber Attach VOAs Laser: Passive Auto-aligned Grating or WDM Coupler Surface Mount PD Active area Developed in collaboration with Enablence WDM Coupler Monitor VOA Laser PIN Future Development WDM Coupler - Wafer scale testing - Flip chip technology for fiber attach 15 VOA APD

16 1Ge CWDM Solution Tx 1 CWDM DFB Lasers hybridized into the Si chip either individually or as a bar Integrated AWG or Echelle grating, to Mux channels together Lasers directly modulated Lasers Detectors Front facet detectors integrated to provide power monitoring VOAs can be integrated to provide power balancing without the need to modify laser drive conditions 6.5nm 12nm Rx Individual PINs or a bar, surface mounted onto wet etched 54 degree vertical coupling mirrors. Demux is integrated into the same chip Fast VOAs can be integrated to improve dynamic range or provide protection DFB λ registration: +/- 2nm 16

17 Kotura s CWDM 1Ge Solution - High level of integration both monolithic (waveguide) and hybrid (micro-bench) - Developed in partnership with Cyoptcis into a very small form factor package Active area PD / Surface mount technology Au:Sn solder 7mm 15mm Monitor / VOAs WDM DFB Array (Cyoptics) BOX p+ n+ Mux / DeMux VOAs 17

18 Fitting 1G into ~1G Footprint! Micro-bench assembly + M De ux + x Mu & 1 x 1G TOSAs 1 x 1G ROSAs Conventional technology Si PLC Tx Chip can not support the footprint Or 1G TOSA 1Ge TxRx Si PLC Rx Chip 1G ROSA Si Solution can support 1G FXP footprint for 1G and offers huge cost saving potential 18 1Ge Module

19 Key Challenges & Merits Key Challenges Low propagation and fiber coupling loss Facet preparation Optical, Electrical & Thermal X-talk Low stress chip attach Thermal management Lead frame Si AWG Ceramic Carrier Fiber Block Key merits Low component count: Integration Low cost fiber attach: V-groove Stress engineering for compensation Thermal tuning Excellent thermal conductivity and temperature uniformity Small foot print Highly scaleable and cost effective manufacturing: CMOS fab Low cost, automated A&T: Wafer scale hybridization and test, Peak and place assembly, Lead frame packaging Simple assembly 19

20 Reliability and Stability Reliability is always a key barrier to deployment of a new technology - Higher integration increases the possibility and consequences of failure - Takes time and a lot of hard data Si is a proven Technology platform: - Well known material system - Solid state switching Real proof is: - Real & qualified products - Tier 1 customers - In live networks carrying traffic Acceleratin factor [-] Predicted mean life based on 85/85 life tests a=.5, n=2,.24 kg water per kg dry air AF = e E k 1 n n ( ) + a( Rt Ru ) 1 ( ) Tu Tt Ayring acceleration model Mean life over 35 years AF (2,5Hr) ML [yr] Activation Energy [ev] Mean life (3, hr test) 2 Delta IL (db) Damp Heat (85C - 85% RH) in-situ monitoring 4 VOA channels 5 hr for qualification and 2, hrs for information Time (hours)

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