A 3.9 ns 8.9 mw 4 4 Silicon Photonic Switch Hybrid-Integrated with CMOS Driver

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Gwendoline Grace Parrish
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1 A 3.9 ns 8.9 mw 4 4 Silicon Photonic Switch Hybrid-Integrated with CMOS Driver A. Rylyakov, C. Schow, B. Lee, W. Green, J. Van Campenhout, M. Yang, F. Doany, S. Assefa, C. Jahnes, J. Kash, Y. Vlasov IBM T.J. Watson Research Center, Yorktown Heights, NY

2 Outline Motivation Silicon photonics technology overview Integration strategies: full monolithic and hybrid 4 4 switch hybrid-integrated with CMOS driver Conclusion 2

3 Motivation Goal: develop photonic device process compatible with CMOS enables high-speed, high-density interconnects for lower power, lower cost, long reach communication opens up a number of new applications (biomedical, sensor, etc) Hybrid integration (flip-chip or wirebond) of Si photonic devices and electrical circuits: ideal for early prototyping important step towards full integration either hybrid or monolithically integrated could be commercialized A 4 4 switch requires the development of all key components, highlights the advantages of the silicon photonic technology: data stays in the optical domain multiple data streams routed in the same device (WDM) 3

4 Outline Motivation Silicon photonics technology overview: Waveguides ( SOI photonic wires ), other passive devices Modulators, detectors Fiber coupling Integration strategies: full monolithic and hybrid 4 4 switch hybrid-integrated with CMOS driver Conclusion 4

55 µm) Undoped Si and SiO 2 are transparent for λ =.2 µm 6.

5 Silicon Photonic Waveguide.5 µm Si (n=3.5).2 µm SiO 2 (n=.45) 2 µm thick buried oxide (BOX) Waveguide cross-section color-coded with intensity of electric field (λ =.55 µm) Undoped Si and SiO 2 are transparent for λ =.2 µm 6.5 µm (this range covers the long haul optical communication C-band) Si surrounded by SiO 2 forms a dielectric waveguide (similar to single mode fiber, but much smaller due to high contrast ratio) Losses (2 µm BOX) : ~2 db/cm and ~. db/bend (R ~5 µm) 5

6 Y-junction: Silicon Photonic Passive Devices split merge Directional coupler: IN T.3 µm coupling length T 2 Ring resonator: IN THRU Ring resonator can be used as add/drop for WDM DROP 6

7 Mach-Zehnder Interferometer Based Modulator IN p-i-n diode phase shifter ON/OFF φ T P P OUT IN = + cos( φ) 2 T 2 5% directional couplers Mach-Zehnder interferometer (MZI) splits the signal into two arms, adds relative phase and then merges the arms again One MZI arm contains a p-i-n diode that implements an optical phase shift through charge injection 7

MZI Modulator with Integrated p-i-n Diode Cross section of one MZI arm shows the partially etched rib waveguide with p-i-n diode 5 µm p-i-n diode phase shifter (L = 2 µm) T IN 5% directional coupler

8 MZI Modulator with Integrated p-i-n Diode Cross section of one MZI arm shows the partially etched rib waveguide with p-i-n diode 5 µm p-i-n diode phase shifter (L = 2 µm) T IN 5% directional coupler 5 nm T 2 The p-i-n diode injects charge into the core of the waveguide, resulting in optical phase shift without significant loss of signal Cu NiSi Si 3 N 4 light charge Si Cu W p i n W. Green, et al. (27); J. Van Campenhout, et al. (29) 8

9 Waveguide Coupled Germanium Detector Cross section Performance: 4 Gb/s (at 2 V bias) Die photo Ge photodetector in CMOS compatible process Speed: 4 Gb/s Size: 2 µm long (~ ff ) Avalanche gain demonstrated at.5 V S.Assefa, et al. (Nature 2) 9

10 Edge Coupling to Standard Fiber SiON couplers over tapered Si waveguides help mitigate the cross-section mismatch: Si waveguide (.2 µm.5 µm) SiON waveguide ( µm 3 µm) single mode fiber core (9 µm diameter) pitch mismatch: Y. Vlasov, et al. (23) parallel fiber array (25 µm pitch) Si waveguide array (2 µm pitch)

µm pitch) 8 Tb/s/mm bandwidth density at chip edge Less than db coupling loss obtained from

11 Optical Coupling to Parallel Waveguides: 64 Gb/s: 4λ in 4 waveguides at 4 Gb/s input 53 nm 537 nm 543 nm 549 nm WG WG 2 WG 3 WG 4 ps Multichannel tapered coupler interfacing Si waveguides (2 µm pitch) 8 Tb/s/mm bandwidth density at chip edge Less than db coupling loss obtained from tapered glass waveguide (through SiON coupling structure) to Si waveguide B. G. Lee, et al. (OFC 2)

12 Outline Motivation Silicon photonics technology overview Integration strategies: full monolithic and hybrid Monolithic integration technology announced (SEMICON 2) 5 Gb/s detector hybrid-integrated with CMOS receiver (CLEO 2) 8 Gb/s ring modulator hybrid-integrated with CMOS driver (OFC 2) 4 4 switch hybrid-integrated with CMOS driver Conclusion 2

CMOS Integrated Nanophotonics Fully integrated 6-channel WDM transceiver project (28): 3 nm design rules for CMOS circuits 65 nm design rules for photonic devices CMOS FEOL integrated (Ge-first prior

13 CMOS Integrated Nanophotonics Fully integrated 6-channel WDM transceiver project (28): 3 nm design rules for CMOS circuits 65 nm design rules for photonic devices CMOS FEOL integrated (Ge-first prior to activation) Small lithographic variations.5 mm 2 per transceiver channel Current focus: transfer to next-generation CMOS W. Green, et al. (SEMICON 2) S. Assefa, et al. (talk OMM6 at OFC 2) 3

14 5 Gb/s Germanium Photodetector Hybrid- Integrated with 9 nm CMOS Receiver Measured 5 Gb/s eye diagram BER < -2 at -8 dbm, 3 nm CMOS Receiver Schematic: Packaged PD+RX: V DD_TIA V DD_LA V DD_IO PD TIA Predriver _ LA Output Buffer CMOS RX Both the PD and the CMOS RX are faster than 5 Gb/s Slowdown attributed to packaging parasitics B. G. Lee, et al. (CLEO 2) 4

15 8 Gb/s Ring Modulator Hybrid-Integrated with 9 nm CMOS -tap FFE Driver Size Power FFE design 8 Gb/s operation (only Gb/s without equalization) FFE Driver Block Diagram: Drive voltage Ring Modulator MZI Modulator (27) 5 µm 2 µm.8 pj/bit 5 pj/bit 5 mvpp 7 Vpp fully integrated discrete components Packaged Transmitter: Tap Buffer Photonic chip fiber Delay In LA Out CMOS IC wirebond Main Buffer J. Rosenberg, et al. (talk OWQ4 at OFC 2) 5

16 Outline Motivation Silicon photonics technology overview Integration strategies: full monolithic and hybrid 4 4 switch hybrid-integrated with CMOS driver 2 2 switch performance 4 4 switch architecture Circuit and package considerations Testing results Conclusion 6

17 IN φ MZI Based 2 2 Switch p-i-n diode phase shifter ON/OFF T ON/OFF IN T transmission (db) T 2 5% directional couplers 3 nm - -8 db wavelength (µm) ON OFF T OFF T 2 ON 5 µm IN ON/OFF T T 2 T 2 J. Van Campenhout, et al. (2) 7

18 Measured Optical Switching Times of a CMOS Driven 2 2 MZI switch ON/OFF ON/OFF normalized power IN OFF T T 2 T, T 22 IN 2 ON ON OFF time (ns) T 2, T 2 time (ns) t /9 = 3.9 ns t /9 =.4 ns B. G. Lee, et al. (CLEO 2) T 2 T 22 8

19 4 4 Switch and CMOS Driver Block Diagram W IN N OUT N IN E OUT CMOS chip Serial Interface 33 µm 52 µm W OUT S IN S OUT E IN E IN S IN MZI 3 MZI 6 model W OUT N OUT Photonic chip W IN N IN MZI 2 MZI MZI 5 MZI 4 function E OUT S OUT 9

20 4 4 Switch Configuration States Of the 2 6 =64 possible states of the 2 2 switches, only 9 are unique. The equivalent states of the 4 4 switch differ by static power dissipation (number of 2 2 switches ON ) In all 9 configuration states, worst case crosstalk between channels is less than - db, insertion loss ~6 db, off chip coupling loss ~ db. State MZI MZI2 MZI3 MZI4 MZI5 MZI6 Power E IN S IN W IN N IN MZI3 MZI2 MZI Area: 3 6 µm 2 (relaxed layout) MZI6 MZI5 MZI4 W OUT N OUT E OUT S OUT 2

from serial interface Digital 9-nm CMOS Driver 33 µm 52 µm 2 6 R CONTACT C(Q) I(τ) p-i-n diode model CMOS chip 2 6 Photonic chip Electrical performance of the CMOS driver V DD =.

21 from serial interface Digital 9-nm CMOS Driver 33 µm 52 µm 2 6 R CONTACT C(Q) I(τ) p-i-n diode model CMOS chip 2 6 Photonic chip Electrical performance of the CMOS driver V DD =.2 V 5 ps ON/OFF optical function Electrical model of the p-i-n diode includes contact resistance, non-linear charge-dependent capacitance and carrier lifetimedependent current source Designed to drive a wide range of capacitive loads and steady state currents with ample speed for switch applications 2

22 4 4 Switch and CMOS Driver Die Photos Serial Interface Drivers with predrivers 5 µm East South West North West North East South 22

Hybrid Packaging of CMOS and Photonics IC probe pads on bottom (not visible) CMOS IC optical coupling Solder Transfer 75 µm pads, 5 µm pitch ~5 µm tall Photonic chip ~3 µm tall Ni-Au Pad

23 Hybrid Packaging of CMOS and Photonics IC probe pads on bottom (not visible) CMOS IC optical coupling Solder Transfer 75 µm pads, 5 µm pitch ~5 µm tall Photonic chip ~3 µm tall Ni-Au Pad Metallization: Photonic chip pads CMOS chip pads solder reflowed again to collapse columns into balls Flux-Free Solder Process: eutectic SnPb solder (26-3 C) plus forming gas ~25-3 g/bond obtained 23

Infrared Images of Static Optical Switching East

Output South Output West Output North Output East

24 Infrared Images of Static Optical Switching East Input East Input East Input All 6 MZI s OFF West Output MZI 6 ON (.2V) North Output MZI 2 ON (.5V) South Output West Output North Output East Output South Output West Output North Output East Output South Output West Output North Output East Output South Output 24

25 53 nm Measured routing of 4 Gb/s data 4 Gb/s modulator 4 4 Photonic Switch EDFA λ att RX North Input South Input East Input West Input North Output No U-Turn South Output No U-Turn East Output No U-Turn West Output No U-Turn 25

26 Measured routing of 3 4 Gb/s WDM data 53 nm 537 nm 4 Gb/s modulator 4 4 Photonic Switch EDFA EDFA λ att RX 543 nm 53 nm 537 nm 543 nm East Input North Output South Output West Output 26

27 Measured Power Sensitivity Curves All wavelength channels, all output configurations of the 3 4 Gb/s signal tested, showing ~.5 db spread at -2 BER 27

28 Conclusion Full set of CMOS compatible photonic devices: waveguides, splitters, couplers, crossings, WDM structures, etc. waveguide coupled integrated Ge photodetectors MZI and ring based switches, modulators High-density, low-loss edge fiber coupling demonstrated 8 parallel fibers coupled to on-chip waveguides on 2 µm pitch Monolithically integrated technology announced in December 2 Recent CMOS driven hybrid-integrated results include a 5 Gb/s receiver and a ring modulator based 8 Gb/s transmitter Hybrid-integrated packaging process developed Hybrid-integrated CMOS driven 4 4 switch fully tested The authors gratefully acknowledge support from DARPA under contract HR-8-C-2. 28

A 24-Channel 300 Gb/s 8.2 pj/bit Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single Holey CMOS IC

A 24-Channel 300 Gb/s 8.2 pj/bit Full-Duplex Fiber-Coupled Optical Transceiver Module Based on a Single Holey CMOS IC A. Rylyakov, C. Schow, F. Doany, B. Lee, C. Jahnes, Y. Kwark, C.Baks, D. Kuchta, J.