Si photonics for the Zettabyte Era. Marco Romagnoli. CNIT & TeCIP - Scuola Superiore Sant Anna

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1 Si photonics for the Zettabyte Era Marco Romagnoli CNIT & TeCIP - Scuola Superiore Sant Anna Semicon 2013 Dresden 8-10 October 2013

2 Zetabyte era Disaggregation at system level Integration at chip level Optical interconnection at shorter reach Electronics-photonics convergence Cost, energy and bandwidth density Architecture, components, SW programming Make it happen or end the information age

3 Example of applications Active Optical Cable Wireless communications 100GE Optical Interfaces (CFP, CXP, CPAK, QFSP,..) Optical switching Inter Chip and Board Level Interconnection

Thunderbolt, new version based on optical cable up to 30m long Sumitomo Electric Industries have been certified by Intel for manufacturing AOC s 10, 20, and 30 mts long.

4 Thunderbolt, new version based on optical cable up to 30m long Sumitomo Electric Industries have been certified by Intel for manufacturing AOC s 10, 20, and 30 mts long. This allows high speed and possibility of connection over distances greater than 1 mt Interestingly a blue ray download at 10 Gb/s occurs in 30 s, at 100Gb/s this would happen in 3 s! Si Photonics could be the technology that allows 100G interconnection at the cost of actual 10G AOC s. In principle 100G at same cost is feasible in the next future

Silicon photonic use in products in near term Si photonics for optical

high capacity, reduced footprint and cabling, very large volumes Key

for high density intra-system interconnect (DU-RRU in RBS and

CPRI (for RBS fronthaul) and Ethernet signals will be supported Next:

5 Silicon photonic use in products in near term Si photonics for optical interconnection Radio Base Station and Router: low cost, low power, high capacity, reduced footprint and cabling, very large volumes Key devices: Up to 10 km long links, 10 Gb/s parallel optics transceivers for high density intra-system interconnect (DU-RRU in RBS and inter-rack connection in Routers). CPRI (for RBS fronthaul) and Ethernet signals will be supported Next: 4x25 Gbps transceivers, parallel optics or WDM, for intra-system interconnect as evolution of the 10 Gbps to scale up the capacity.

6 Optical Interfaces for Different Network Platforms Datacom (CXP, CPAK) Telecom (CFP) Data center access Data center aggregation Edge routing Core routing The Optical challenges: Bandwidth Density Cost Consumption

Using the CFP4, up to 16, 100Gbps modules will fit on a blade, a total line rate of 1.6 Tb/s.

7 The CFP (C Form-Factor Pluggable) optical module to enable Terabit blades or line-cards The next-generation CFP modules - the CFP2 and CFP4 (10/40 km) multiplies the number of 100 Gb/s optical module interfaces on a blade. Using the CFP4, up to 16, 100Gbps modules will fit on a blade, a total line rate of 1.6 Tb/s. With a goal of a 60W total module power budget per blade, that equates to 27Gb/s/W. In comparison, the power-efficient SFP+ achieves 10Gbps/W.

8 T T T T T T Optical switching for Add Drop Multiplexing Field of application: lightpath reconfiguration in Metro-access and Access network (e.g. mobile backhaul) Cost: low Footprint: miniaturized T T T Mini- ROADM Mini- ROADM Mini- ROADM Mini- ROADM T T T

9 Inter Chip and Board Level Interconnection Case study: «Optical PCIe3.0» working group within the Communication Technology Roadmap (CTR4) of the Microphotonics Center Consortium (MPhC) at MIT

10 Chip to Memory Interconnection Interconnection through Si interposer

11 Technology

12 Electrical Interconnect Limitations Bandwidth Limitations Wires are not scalable. Bandwidth is fundamentally limited by the available area Power Limitations - Total interconnect power is high ~50% of Total Chip Power Expected to rise to >80% (limit 200W). Signal Integrity and Latency Limitations RC Delay will increase considerably with scaling Al/Oxide + Gates Al/Oxide Sam Naftziger, AMD fellow 2011 VLSI Symposium Keynote Cu + Gate Cu Gate

13 Photonic Electronic Layer - 3D Integration 3D integration of SOI technology for the photonic layers with Si CMOS technology for the circuit layers. Integration in a 65nm node/12 fab based on wf/wf or wf/die bonding and low capacitance TSV technology. Bond Pads Si Logic Layer TSV Si TSV Thermal Compression Bonding SOI Photonics Layer PD Mod Si waveguide Substrate 13

Si Interposer Si Interposer Si Optical Interposer Coupler Micro Bumps Silica Waveguides Heat Sink 100nP m + Photonic Electronic Layer Metal Pad / via 480n 220n m P N m N + N + MZI Modulat or Oxide N

14 Si Interposer Si Interposer Si Optical Interposer Coupler Micro Bumps Silica Waveguides Heat Sink 100nP m + Photonic Electronic Layer Metal Pad / via 480n 220n m P N m N + N + MZI Modulat or Oxide N Micro Bumps P Si Substrate P + BOX P G e N+ Silicon + Waveguide Ge Photodetect or Silicon Waveguides, resonators, detectors 1.5um Optical Fiber I/O HMC ASIC HMC Interposer Package Redistribution layer Flip Chip Bumps BGA Balls Interpose / Photonics Layer TSV Redistribution Layer

Si Photonics - Advantage of full integration Cost: photonic-electronic

Save in packaging, wire bonding and traces/pin-out.

Node scalability, low consumption and improved yield.

15 Si Photonics - Advantage of full integration Cost: photonic-electronic chip (development, mask set, wafers, manufacturing). Save in packaging, wire bonding and traces/pin-out. Technology: low capacitance 3D integration. Node scalability, low consumption and improved yield. Performances: trade off between consumption, size, IL and link/system specs Maturity of individual components: to be improved but not conceptually limited. Photonic chip 15

16 Si Photonics Full integration: Integrated Laser Source Hybrid mounting III-V: conventional solution. It can be butt coupled or coupled through grating coupler. Coupling loss 1 3dB, TEC, Packaging, assembly. Cost and large consumption. Uncooled is preferred. VCSEL: conventional solution for <100m reach. Good for power consumption, temperature stability, packaging and cost. Drawback: MM interconnection Single mode VCSEL are now becoming available. Bonded III-V Laser: remarkable solution at initial stage of R&D. Industrialization to be demonstrated. Threshold current and reliability to be improved. Ge Laser: The only monolithic solution. Potential good performance (power and threshold). Large gain BW and wide tunability. Best operation at high T ( C). To be developed. 16

Aurrion Hybrid Silicon Platform bonds III/V wafer or die

couples to III/V optical gain, detection or modulation

17 Aurrion Hybrid Silicon Platform bonds III/V wafer or die to silicon. 150-mm wafer bonding and processing possible; III/V processed in low-temperature backend process; Mode couples to III/V optical gain, detection or modulation from III-V Material. Fujitsu Hybrid III/V SOA mounted on Si Platforrm; Mode butt couples to III/V optical gain Fujitsu

19 Technological challenges Parameters to be improved Link loss budget Laser consumption Laser cooling Laser operating temperature Thermal impedance Cost Targets Medium/short reach 100G Ethernet 100GE LR4 & SR4: CFP4 and QFSP 400GE nr16 & SR16: CFP4x4 I/O: 16x 25G (CDAUI, NRZ) CFP2 I/O: 8x 50G (CDAUI-8, PAM-4 or NRZ) RBS-DU 10G up to 10km Others Short reach Multi Chip Module Bandwidth scalability Bandwidth density/area (e.g. 30Tbps/cm 2 )

20 Conclusions Assuming Maturity of Si Photonics low consumption, good performance, component availability Early stage of photonics electronics integration Needs Low consumption, uncooled operation laser integration evolution Photonic Electronic convergence through Si optical interposer (3D integration, TSV s interconnections) Result Huge energy saving Latency control Increase of BW density Miniaturization Lower costs Zetabyte Era

21 thank you!

Opportunities and challenges of silicon photonics based System-In-Package

Opportunities and challenges of silicon photonics based System-In-Package ECTC 2014 Panel session : Emerging Technologies and Market Trends of Silicon Photonics Speaker : Stéphane Bernabé (Leti Photonics