PERSPECTIVES FOR DISRUPTIVE 200MM/8-INCH GAN POWER DEVICE AND GAN-IC TECHNOLOGY DR. DENIS MARCON SR. BUSINESS DEVELOPMENT MANAGER

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1 PERSPECTIVES FOR DISRUPTIVE 200MM/8-INCH GAN POWER DEVICE AND GAN-IC TECHNOLOGY DR. DENIS MARCON SR. BUSINESS DEVELOPMENT MANAGER

2 What I will show you today 200mm/8-inch GaN-on-Si e-mode/normally-off technology is ready Epitaxy is available to cover applications (at least) till 650V E-mode/normally-off technology has solved all the issues Vth vs Ron, Gate Leakage, Dynamic Ron-Dispersion, Reliability,... Available to you via tech-transfer or private full lot...what is next? GaN-IC: Full GaN power-ic monolithically integrated in one chip Revolution in GaN technology enabled by means of GaN-on-SOI and isolation technologies Half-bridge with integrated driver and Logic Available to everyone via MPW offering 2

3 3 200MM/8-INCH GAN-ON-SI E-MODE/NORMALLY-OFF TECHNOLOGY IS READY

4 200mm/8-inch GaN-on-Si epi-challenges Some of the key issues (for non-optimized epi) The Si lattice is 17% larger than the GaN lattice Coefficient of thermal expansion (CTE) mismatch between GaN and Si is 116% NON OPTIMIZED GaN-on-Si Epitaxy technology GaN layer cracking Low mechanical stability (i.e. wafer breakage) excessive wafer bow (>50µm)

5 Wafer warp (µm) Imec s 200mm/8-inch GaN-on-Si buffers Imec has solved all the epi-related issues +50µm GeN2-HV buffer -50µm GeN1-HV buffer LV buffer Imec GaN-on-Si buffer Within Warp specs Mechanically strong High surface quality High performance Dispersion free Reliable 5

6 Architectures for Normally-off/E-mode GaN devices Two architecture families can be identified for e-mode device p-gan HEMT Recessed MISHEMT S AlGaN G p-gan D S in-situ G Si 3 N 4 AlGaN D 2DEG GaN 2DEG GaN A p-gan layer below the gate liftup the band diagram below the gate to realize e-mode operation. The AlGaN layer is recessed below the gate, to locally interrupt the 2DEG to realize e-mode operation. 6

7 Source metal 1 field plate Choice of Gate architectures Stacked gate patterning Separate gate patterning SiO 2 Source contact field plate SiO 2 Gate Metal Gate metal field plate SiO 2 TiN p-gan AlGaN SiO 2 TiN interlayer p-gan AlGaN barrier GaN channel One-step processing of p-gan and gate metal Simple process High gate metal sheet resistance Absence of Gate Field Plate Separate patterning of p-gan layer and gate metal TiN interlayer protects the p-gan surface Lower gate metal sheet resistance Possibility to have Gate Field Plate 7

8 Optimum Transistors Performance: identification of the center point Center point Buffer Buffer type Imec s buffer GaN channel AlGaN barrier Thickness XX nm Thickness / Al % XX nm / XX % Epi and device processing have been optimized for performance (Vth, Ron, leakage...), reliability and manufacturability Buffer p-gan epi Layer thickness XX nm Mg chemical level XX at/cm 3... Barrier Temperature growth / activation Pressure XX C Process Gate metal XX p-gan selective etch XX Torr XX Dielec. access region Center point P-GaN layer dep Dielectric access region Dielectric back-end XX XX P-GaN Dry etch 8

9 V t (V) Optimization of Transistors Performance Several epi and device parameters needs to be tuned together V 7.5 Ohm.mm R on (Ohm.mm) Barrier DOEs Identification of the best point for high Vth and Low Ron Dielectric 1 Dielectric 2 2DEG R sh V t R on Dyn R on Type 1 SiN Type 2 SiN Type 2 SiN Type 2 SiN Type 1 SiO 2 Type 2 SiO 2 Al% 25.0% Type 3 SiO 2 Type 2 SiO 2 Al% 22.5% Type 1 Al Al% 20.0% 2 O 3 Type 2 SiO 2 Al% 17.5% Type 1 HfO 2 Type 2 SiO 2 Type 1 Al 2 O 3 /HfO 2 Type 2 SiO 2 Identification of the best dielectric combinations 9

10 Forward Gate Leakage optimization Aim is to push the technology for large gate breakdown and reliability DOE V gs ~ 5 V DOEs to optimized the Gate leakage without impacting Vth (and Ron) With latest optimization, hard breakdown is beyond 10V HTGB at 150C test passed at Vg=+7V 10

11 Norm. dynamic R on at 200 V Normalized Dynamic Ron Normalized Dynamic Ron Optimization towards less than 20% Dynamic Ron All matter to lower Dynamic Ron: Epitaxy, Design, Gate, Dielectric etc Normalized dynamic R on at 198 V DOEs to identify best conditions Fine tuning 25 deg C 150 deg C 150 nm + SiN 180 nm + SiN 260 nm + SiN 180 nm + SiO2 DOES for optimization SiO 2 layer thickness (nm), back-end dielectric Today Dynamic Ron is less than 20% up to 650V (both at RT and at 150C) 11

12 Imec s 200mm p-gan e-mode transistors: output characteristics 200mm GaN-on-Si power transistors (36mm powerbar) for 650V applications Ids Design C3 T=150C In collaboration with On Semiconductor Ig 1µA/mm E-mode output characteristic >2000 HRS HTRB stress <1uA/mm up to 650V at Vg=0V Hard breakdown beyond 1000V 12

13 Technology Transfer Transfer of state-of-the-art technology to slash time-to-market Imec provides detailed transfer documentation Engineers will follow one or more lot(s) step-by-step and absorb imec s know-how Imec provides remote support 8 working-days 2 months Class room training Hands-on training 9 months Remote support Install process at Customer side by customer T0 T0+3months T0+12 months Transfer plan and activities is defined together with the customer based on customer s needs 13

14 Private Lot To obtain 12 wafers with your design into imec s state-of-the-art GaN e-mode technology Imec provides PDK: 100V, 200V or 650V e-mode transistors (or diode) Customer designs power devices into imec s PDK Imec can provide assistance Dedicated mask is taped out 12 wafers are processed, characterized and delivered Imec commits to meet specs (on imec s design) Imec provides PDK Customer provides GDS-II file Mask tape-out Lot processing (12 wafers) 3 weeks 16 weeks 14

15 GAN-IC: FULL GAN POWER-IC MONOLITHICALLY INTEGRATED IN ONE CHIP

16 How does introducing GaN-IC fell like? A revolution in power technology Si discrete devices technology GaN discrete devices technology Imec s GaN-IC technology Evolution of power conversion technology

17 Revolution in GaN Power Technology Monolithically (fully) integrated GaN-IC Power convertor are still formed by discrete: Bulky system Not taking advance of GaN (high f) performance Hampered by parasitic Costy (many packaged devices) Very limited flexibility Monolithically (fully) integrated GaN-IC Compact system Unlock the full potential of GaN tech Low parasitic Cheaper (no need for packages) Very flexible Foster innovation

18 Full GaN-IC is NOT possible on GaN-on-Si Devices are connected via the substrate This is the problem Half-bridge integration is not possible on a regular silicon substrate because there is only one substrate reference. 18

19 GaN-IC requires a buried oxide GaN-on-Si IMEC Solution for GaN-IC GaN-IC technology requires a buried oxide combined with trench isolation. Each transistor has it s own isolated pocket with a separate source connected to the substrate 19

20 Si(111) Cross-talk/Backgating effect is eliminated with imec s GaN-IC technology (a) (b) Norm. I D Low side S1 V B-S1 =0V 1.4 S1 1.2 G1 p-gan AlGaN Substrate contact B1 V B1-S1 =0V G1 p-gan AlGaN (Al)GaN D1 D1 V SW N Implantation B V SW (a) GaN-on-Si Trench High side S2 S2 V B2-S2 =0V G2 p-gan AlGaN V B-S2 <0V Si(111) G2 p-gan AlGaN Subs. B grounded V S2 = 0 V 100 V 200 V (Al)GaN Si(111) SiO 2 Si(100) D2 D2 B2 V G2S2 =5V V D2S2 =1V Stress time (s) V IN V IN Norm. I D (a) GaN-on-Si V S2 = 0 V Subs. B floating 100 V 200 V V G2S2 =5V V D2S2 =1V Stress time (s) (b) V B-S1 =0V Norm. I D S1 Substrate contact B G1 p-gan AlGaN V B1-S1 =0V (Al)GaN (b) GaN-on-SOI Subs. B2 connect. to S2 100 V D1 200 V V S2 = 0 V Trench V SW S2 V B2-S2 =0V I D reduction is eliminated. V G2S2 =5V V D2S2 =1V B Stress time (s) V B-S2 <0V G2 p-gan AlGaN (Al)GaN Si(111) SiO 2 Si(100) D2 B2 V IN 20

21 GaN-IC: Layout examples and logic LOGIC Resistor Transistor Logic (RTL) H3 R H1 H2 R L H6 H5 H4 HS H1 H2 H3 R H Inverter NOR LS NAND Power device with integrated driver Half-bridge LS RS Flip Flop Further functionality will be added: Analog/digital low voltage devices integrated diodes, d-mode devices T-sensors... Half-bridge with integrated driver 100-MHz 17-stage ring oscillator 21

22 GaN-IC: it is accessible to everybody via imec s MPW offering 200V GaN-IC 650V GaN-IC 200V GaN-IC + integrated diode 200V 650V GaN-IC + integrated diode 200V GaN-IC + diode + d-mode 650V 650V GaN-IC + diode + d-mode Imec s roadmap for GaN-IC 200V GaN-IC PDK Released Deadline for GDS-II submission DRC Checks 1 st Shuttle Delivery of Dies Next Shuttles... Feb 2019 May 2019 August 2019 October 2019 Design environment: Cadence Virtuoso Mentor Calibre MPW: Die size: 5.15 x 5.15 mm 2 / 20 dies delivered 22

23 What I showed you today 200mm/8-inch GaN-on-Si e-mode/normally-off technology is ready Epitaxy is available to cover applications (at least) till 650V E-mode/normally-off technology has solved all the issues Vth vs Ron, Gate Leakage, Dynamic Ron-Dispersion, Reliability,... Available to you via tech-transfer or private full lot...what is next? GaN-IC: Full GaN power-ic monolithically integrated in one chip Revolution in GaN technology enabled by means of GaN-on-SOI and isolation technologies Half-bridge with integrated driver and Logic Available to everyone via MPW offering 23