MEMRISTOR DEVICES: FABRICATION, CHARACTERIZATION, SIMULATION, AND CIRCUIT DESIGN. Thesis. Submitted to. The School of Engineering of the

Transcription

1 MEMRISTOR DEVICES: FABRICATION, CHARACTERIZATION, SIMULATION, AND CIRCUIT DESIGN Thesis Submitted to The School of Engineering of the UNIVERSITY OF DAYTON In Partial Fulfillment of the Requirements for The Degree of Master of Science in Electrical Engineering By Chris Yakopcic Dayton, Ohio August, 211

2 MEMRISTOR DEVICES: FABRICATION, CHARACTERIZATION, SIMULATION, AND CIRCUIT DESIGN Name: Yakopcic, Chris APPROVED BY: Tarek M. Taha, Ph.D. Advisory Committee Chairman Associate Professor Electrical and Computer Engineering Guru Subramanyam, Ph.D. Committee Member Chair and Professor Electrical and Computer Engineering Andrew Sarangan, Ph.D. Committee Member Associate Professor Electro-Optics John G. Weber, Ph.D. Associate Dean School of Engineering Tony E. Saliba, Ph.D. Dean, School of Engineering & Wilke Distinguished Professor ii

3 Copyright by Chris Yakopcic All Rights Reserved 211 iii

4 ABSTRACT MEMRISTOR DEVICES: FABRICATION, CHARACTERIZATION, SIMULATION, Name: Yakopcic, Chris University of Dayton Advisor: Dr. Tarek M. Taha AND CIRCUIT DESIGN Significant interest has been placed on developing systems based on memristors since the initial fabrication by HP Labs in 28 [1]. The memristor is a nanoscale device with dynamic resistance that is able to retain the last programmed resistance value after power is removed from the device. This property shows that the memristor can be used as a non-volatile memory component, and has potential to enhance many types of systems, such as high density memory, and neuromorphic computing architectures. This thesis presents the fabrication and characterization results obtained based memristor devices developed at the University of Dayton. In addition, a comparison between the existing memristor device models was completed to show how the memristor can be used in a multistate operation. Lastly, circuit designs were completed that demonstrate the writing and reading of information to and from memristor devices. These represent the initial steps required in developing electronic systems based on memristors. A large portion of the work completed in this thesis has been published in [2-4]. iv

5 ACKNOWLEDGMENTS My special thanks are in order to Dr. Tarek M. Taha, my advisor, for providing the time and equipment necessary for the work contained herein, and for directing this thesis and bringing it to its conclusion with patience and expertise. I would also like to express my appreciation to everyone who has helped me with this work. This includes Dr. Andrew Sarangan and Dr. Eunsung Shin, who were responsible for fabricating the devices characterized in these experiments; Dr. Guru Subramanyam and Dr. Douglas Hansen, who provided the necessary equipment for characterizing the devices; and Mark Patterson, who offered his help and expertise when designing the mask set used for the second device fabrication experiment. v

6 TABLE OF CONTENTS ABSTRACT... iv ACKNOWLEDGMENTS...v LIST OF FIGURES... ix I. INTRODUCTION...1 II. BACKGROUND Memristor Origin Physical Memristor Discovery HP Labs Titanium Dioxide Memristor Alternative Thin-Film Memristor Designs Spintronic Memristor Devices RRAM Device Modeling Circuit Design Applications III. PHYSICAL DEVICE EXPERIMENT Device Fabrication vi

7 3.2 Experimental Test Setup Experimental Test Results Characterization by User Controlled Test Setup Characterization by Computer Controlled Test Setup Characterization Using Pulse Waveform IV. PHYSICAL DEVICE EXPERIMENT Mask Design for Future Devices Overall Mask Set Device Patterns in Mask Design Second Generation Device Fabrication Second Generation Device Characterization V. COMPARISON OF DEVICE MODELING METHODS Modeling Equations Equation Based Device Simulation Device Simulation Based on Linear Model Device Simulation Based on Non-Linear Model Device Simulation Based on Non-Linear Model Resistance State Analysis Based on Device Models Resistance States in the Linear Device Model Resistance States in the Non-Linear Device Models vii

8 5.3.3 Resistance State Comparison Device Modeling Based on Fabrication Data... 5 VI. CIRCUIT DESIGN BASED ON NON-LINEAR DRIFT MODEL Circuit for Writing to Memristor Write Circuit Schematic Simulation Results for Memristor Write Circuit Circuit for Reading Resistance of a Memristor Device Read Circuit Schematic Simulation Results for Memristor Read Circuit VII. CONCLUSION...59 BIBLIOGRAPHY...62 viii

9 LIST OF FIGURES 3.1. Device layout for UDMEM Device layout for UDMEM Device layout for UDMEM Memristors on wafer: (a) alignment of multiple memristors on a wafer, and (b) probe applied to test a single device Test results for UDMEM1 with a voltage loop ranging from -4V to 4V Test results for UDMEM2 with a voltage loop ranging from -4V to 4V I-V curve results for UDMEM2 with voltage ranging from -8V to 5V Multiple voltage loop test, first pass Multiple voltage loop test, second pass Multiple voltage loop test, third pass Test results for UDMEM2 with a voltage from -5 to 5V on the first pass Test results for UDMEM2 with a voltage from -5 to 5V on the second pass Test results for UDMEM2 with a voltage from -5 to 5V on the fifth pass Test results for UDMEM8 with a voltage from -4 to 4V on the first pass Test results for UDMEM8 with a voltage from -4 to 4V on the second pass Test results for UDMEM8 with a voltage from -4 to 4V on the first pass Test results showing the resistance drop across the memristor as a function of the number of voltage pulses applied to the device ix

10 4.1. Layout of entire mask Layout for (a) top metal mask, (b) etch mask, and (c) bottom metal mask Layout of 4 different areas in the mask set including (a) the larger individual devices, (b) the crossbar with 1 µm 2 overlap, (c) the smaller individual devices, and (d) the crossbar with 25 µm 2 overlap Span of devices that are included in the larger device set (25 µm 2 to 4 µm 2 ) Span of devices in the smaller devices set ( µm 2 to 35 µm 2 ) Device layout for second generation memristor device (contact pads not shown) Images of the SiO 2 wafer after Pt deposition displaying (a) the contact pad and wire leading to an isolated device, and (b) the wire passing through the circular definition of a crossbar device Image displaying memristor wafer after deposition of TiO 2 and TiO 2-x layers Images displaying the lithography pattern for the top metal for (a) an isolated device, and (b) a device in a crossbar Images of fabricated wafer displaying (a) portion of a memristor crossbar, and (b) an array of single devices in a wire bonded packaging Test results for the 2µm 2 memristor device Test results for the 1µm 2 crossbar memristor device Simulation results for testing liner drift velocity model. The top left plot shows the current and voltage waveforms with respect to time, and the top right plot shows the I-V characteristic. The bottom left plot shows position of the barrier between the titanium oxide layers and the bottom right plot shows resistance as a function of time. Simulation x

11 parameters are, R ON =1Ω, R OFF =1Ω, D=46nm, µ D =1-14 m 2 V -1 s -1, w /D=.2, with a triangle voltage input where f=2hz and A=.25V Simulation results for testing the Joglekar non-linear drift velocity model with p=1. The top left plot shows the current and voltage waveforms w. r. t. time, and the top right plot shows the I-V characteristic. The bottom left plot shows position of the barrier between the titanium oxide layers and the bottom right plot shows resistance as a function of time. Simulation parameters are, R ON =1Ω, R OFF =1Ω, D=37nm, µ D =1-14 m 2 V -1 s - 1, w /D=.2, with a triangle voltage input where f=2hz and A=.25V Simulation results for testing the Biolek non-linear drift velocity model with p=1. The top left plot shows the current and voltage waveforms w. r. t. time, and the top right plot shows the I-V characteristic. The bottom left plot shows position of the barrier between the titanium oxide layers and the bottom right plot shows resistance as a function of time. Simulation parameters are, R ON =1Ω, R OFF =1Ω, D=32nm, µ D =1-14 m 2 V -1 s - 1,w /D=.2, with a triangle voltage input where f=2hz and A=.25V Plot on the left shows number of resistance levels achieved using the linear drift model for D=9-115nm where R ON /R OFF =1 for current pulse differentials given as 5, 1, and 15%. Plot on the right shows same data for R ON /R OFF =5 and D=42-55nm. Other simulation parameters are, R ON =1Ω, µ D =1-14 m 2 V -1 s -1, w /D=.2, with a triangle voltage input where f=4hz and A=2V Plot on the left shows number of resistance levels achieved using the Joglekar nonlinear drift model for D=6-12nm where R ON /R OFF =1 for current pulse differentials given as 5, 1, and 15%. Plot on the right shows same data for R ON /R OFF =5 and D=3- xi

12 5nm. Other simulation parameters are, R ON =1Ω, µ D =1-14 m 2 V -1 s -1, w /D=.2, with a triangle voltage input where f=4hz and A=2V Simulation results for testing the Joglekar non-linear drift velocity model with p=1. The top left plot shows the current and voltage waveforms w. r. t. time, and the top right plot shows the I-V characteristic. The bottom left plot shows position of the barrier between the titanium oxide layers and the bottom right plot shows resistance as a function of time. Due to the strong memristive effect, device operates as a linear resistor after 1.5s. Simulation parameters are, R ON =1Ω, R OFF =1Ω, D=5nm, µ D =1-14 m 2 V -1 s - 1,w /D=.2, with a triangle voltage input where f=4hz and A=2V Plot on the left shows number of resistance levels achieved using the Biolek nonlinear drift model for D=5-11nm where R ON /R OFF =1 for current pulse differentials given as 5, 1, and 15%. Plot on the right shows same data for R ON /R OFF =5 and D=3-5nm. Other simulation parameters are, R ON =1Ω, µ D =1-14 m 2 V -1 s -1, w /D=.2, with a triangle voltage input where f=4hz and A=2V Comparison of results for resistance level data presented in previous section using a minimum pulse differential of 5% Device conductance as a function of doped layer thickness when using simulations based on equation (1) Simulation results for numerically based model that incorporates programming threshold displaying (a) the voltage input, (b) the memristor state, and (c) the dynamic resistance value MOSFET based memristor write circuit xii

13 6.2. Memristor response to write circuit simulation with voltage applied from V1. Top left plot shows the voltage across the memristor, when the 5V pulses are applied, the top right plot shows the current in the memristor and the voltage pulse are applied, and the bottom plot shows the shift if the state variable w(t) relative to the thickness of the device Memristor response to write circuit simulation with voltage applied from V2. Top left plot shows the voltage across the memristor, when the 5V pulses are applied, the top right plot shows the current in the memristor and the voltage pulse are applied, and the bottom plot shows the shift if the state variable w(t) relative to the thickness of the device Comparator based read circuit for memristor Read circuit simulation. The top plot shows the input voltage, the middle plot shows the voltage generated between the memristor and the 75k resistor, and the bottom plot shows the output of each of the comparators xiii

14 CHAPTER I INTRODUCTION For nearly 18 years, it has been accepted that there are three fundamental passive circuit elements, the resistor (1827), the capacitor (1745), and the inductor (1831). In 1971 Dr. Leon Chua theorized that mathematically there should be a fourth fundamental circuit element based on the symmetry of the equations that govern passive circuit theory [5]. Dr. Chua called this device the memristor (short for memory-resistor), and in 28 Hewlett Packard Labs published results of the device in physical form [1]. The physical memristor is nanoscale device that has unique properties that can be used to greatly improve existing electronic systems and computing architectures. The memristor can be thought of as a time varying resistor where the resistance changes due to the summation of current that has passed through the device [5]. When the current flowing through the device is zero, the summation of current becomes constant, and thus the resistance remains unchanged. This shows that the memristor can be used as a nonvolatile memory component. Furthermore, the dynamics of a memristor closely resemble those of a synapse in brain tissue. Just as the values of synaptic weights change with the application of neural spikes, the resistance value of a memristor can be changed with the application of a voltage pulse. This could provide significant advancements in the field of neuromorphic 1

15 computing as electronic systems using memristors could be fabricated with a device density similar to that of the human brain [6]. Since the memristor s physical discovery, several institutions have published memristor device fabrications using a variety of different materials and device structures [2, 7-13]. Different device structures are still being developed to determine which memristor device would be the best option for commercial use. This is based on many factors such as size, switching speed, power consumption, switching longevity, and CMOS compatibility. Several device models have also been proposed that can be used simulate memristor based circuits [1, 14, and 15]. The circuits published thus far involve methods of writing to and reading from memristors [16-19], and using a memristor based circuit as a component in a neuromorphic system [2, 21]. The memristor devices, memristor models, and basic circuit designs will serve as the first steps in developing electronic systems and computing architectures based on memristors. The work presented in this thesis involves memristor device fabrication and characterization, memristor model comparisons, and read and write circuit designs. Two different memristor fabrication experiments are described. The first was based on a set of wafers containing an array of isolated devices with a large cross-sectional area (375 by 375µm) where each wafer was fabricated with different oxide thicknesses. The results of this experiment showed that the wafer with a total oxide thickness of 1 nm provided the most reliable devices. A large hysteresis pattern could be seen when the device was positively biased. The work based on this experiment was published in [3, 4]. The second memristor fabrication experiment was based on a much more complex wafer. A mask set 2

16 was designed to produce isolated memristor devices with variable cross-sectional area (2.5µm 2 to 4µm 2 ) in addition to small crossbar arrays containing 36 devices at a crosssectional area of ether 25µm 2 or 1µm 2. The results of the wafer based on this design provided a stronger hysteresis pattern in both the positive and negative voltage regimes. A comparison of three existing memristor device models was performed to show how the memristor could be used as a multistate memory device for use in a high density memory system or a synaptic weight in a neural system. The three models compared were published in [1, 14, and 15] and were developed on the basis that a memristor acts as two variable resistors in series where the dynamic resistance component is determined by a state variable. The state variable assigns a numerical value to the physical changes in the device that relate to a change in resistance. The motion of the state variable differs in each of these models. The simulations completed in this experiment examine how many distinguishable resistance values can be observed after a series of voltage pulses are applied to the device model. The results showed that the model in [15] provided the maximum amount of observable resistance levels, although the models have a large amount of discrepancy when comparing to actual characterization data. The work completed based on the model comparisons was published in [2]. An alternative modeling approach was developed based on characterization data provided in [1], and was developed using a lookup table approach. Circuits were then developed to write information and to read information from memristors. Simulations of the circuit designs were performed in SPICE using the memristor model published in [15]. The simulation results for the write circuit show that the state (conductivity) of a memristor can be increased or decreased when a positive 3

17 voltage pulse is applied to one of two inputs. The read circuit shows how a system of comparators can be used to quantize the resistance value of a memristor into a discrete number of states for digital processing. Chapter 2 provides a background section that describes the work completed based on memristors since it was first theorized by Dr. Chua [5]. Chapter 3 presents the fabrication techniques and results for the first memristor fabrication experiment carried out at the University of Dayton. Chapter 4 describes the mask design for the more complex set of memristors along with fabrication information and test results. Chapter 5 shows how existing memristor models and characterization data may be used to predict the behavior of a memristor when used as a multi-state device. Chapter 6 presents circuit designs and simulation results for reading and writing to memristor devices. Lastly, Chapter 7 provides a conclusion of the results. 4

18 CHAPTER II BACKGROUND 2.1 Memristor Origin The memristor was first theorized by Dr. Leon Chua in 1971 [5] as the fourth passive fundamental circuit element. Based on the symmetry of the equations that govern the resistor, capacitor and inductor, Dr. Chua hypothesized that fourth device should exist that holds a relationship between magnetic flux and charge. This would complete the circle where the resistor holds the relation between current and voltage, the inductor holds the relationship between current and flux, and the capacitor holds the relationship between voltage and charge. Dr. Chua proved that the abilities of the memristor could not be duplicated by any of the other three passive elements, and that an active circuit that mimics the functionality of the theorized device would require approximately 25 transistors. The memristor was predicted to be a device with a dynamic resistance that is determined by the integral of current flowing through it. Since this is an integral relationship, applying zero current would result in a constant charge, thus leaving the resistance constant. This shows that the theorized memristor possesses the ability to retain a resistance value even after the power source is removed from the device. Unlike the capacitor and inductor, this is not an energy storage device, so the voltage must equal zero whenever the current goes to zero. This causes the I-V curve of the device to 5

19 produce a pinched hysteresis loop, revealing that the device has a memory effect associated with it. A few years later, Dr. Chua and Dr. Sung Mo Kang, produced further research on the theoretical memristor device, claiming the memristor to be a subset of a broader class defined as memristive systems [22]. Like memristors, all memristive systems must have a zero output whenever the input is zero, and this is what distinguishes them from arbitrary dynamical systems. Chua and Kang found publications dating back to the early 19s that described systems that could be classified as memristive, but this connection had never been realized. The memristor was considered nothing more than a mathematical curiosity until the first successful fabrication of a memristor device was published in 28 [1]. 2.2 Physical Memristor Discovery The first fabrication of a memristor device was developed by a research team at HP Labs lead Dr. Stanley Williams [1]. The research team at HP Labs was formed in 1995, and they initially started working on ways to further increase computing power once transistors reach their minimum size constraint. They decided the solution should be a nanoscale crossbar series of switches, which would be designed so the system could still function even if some of the components were defective [23]. The initial device structure for the switches at each crossbar junction was a layer of platinum dioxide, followed by a monolayer film of switching molecules, and finally a layer of titanium. When considering the platinum crossbars as electrodes, the resulting device was defined within this 5 layer structure. As the internal mechanism in the device 6

20 was studied, it became apparent that the oxygen atoms in the device migrated through the monolayer, and formed titanium dioxide on the other side. They also found that the titanium dioxide was formed in two different patterns, a stoichiometric layer, and a slightly oxygen deficient layer. The monolayer was then removed and a fabrication method was determined that would yield reliable devices that contained both the stoichiometric and oxygen deficient layers of titanium oxide [23]. Testing of these devices showed that the resistance of the device did not change when the voltage source was removed, and although it wasn t circular, the device provided an I-V characteristic in the form of a pinched hysteresis loop [1]. Following this discovery, HP Labs has produced extensive research based on the fabrication, modeling, and dynamics of titanium dioxide memristor devices [24-32] HP Labs Titanium Dioxide Memristor The structure of the thin-film titanium dioxide memristor was decided to be a stoichiometric layer of titanium dioxide (TiO 2 ) and an oxygen deficient layer (TiO 2-x ) sandwiched between two platinum electrodes [1]. The device was determined to be functioning by the migration of the charged vacancies in the oxygen deficient layer. When a positive voltage was applied to the device, the oxygen vacancies expanded. This created a thicker oxygen deficient layer, thus reducing the resistance of the device. Conversely, when a negative voltage was applied to the device, the oxygen vacancies contracted and the resistance of the device increased. HP Labs created a simple mathematical model that described this phenomenon based on two dynamic resistors and a differential equation that modeled the migration of oxygen vacancies [1]. 7

21 HP Labs has since published many more papers based on the characterization of the TiO 2 memristors that they developed [24-32]. One of these papers describes a more complex test setup for characterizing memristor devices [26]. A series of pulses was applied to the device with a constant voltage, but a variable pulse width. This was done to characterize the state variable that determined the resistance of the device. The state variable was then fit to the Simmon s tunneling equation for a metal-insulator-metal (MIM) junction with image forces [33]. The mechanism for resistance change was then described as a tunnel barrier with variable thickness. Further work was done on this device to see if Joule heating had an impact on the resistive switching process of a memristor device [27]. These results also concluded that the resistance change is determined by the modulation of the width of a tunnel barrier. Furthermore, as temperature significantly changed the resistance value, temperature can potentially be seen as a hidden state variable within the device. Dr. Paul Strachan et al. published a paper that describes the electroforming process in the memristive devices [3]. These devices were fabricated using TiO 2 sandwiched between two platinum electrodes. The application of a high voltage changed the makeup of the device, leaving a bubble of oxygen deficient material in the thin-film. The TiO 2-x channel formed only in a small portion of the device, and a small layer of TiO 2 was left between the oxygen deficient channel and the platinum conductor which supports the possibility of a tunnel gap. Dr. Strachan et al. described the oxygen deficient layer as possibly having a crystal structure of Ti 4 O 7, [32]. These results were supported by a group led by Dr. Deok-Hwang Kwon at Seoul National University as they found the same crystal structure present in their devices [34]. 8

22 2.2.2 Alternative Thin-Film Memristor Designs Since HP labs discovered the memristor, several academic institutions, including the University of Dayton, have published results of memristor devices. These devices show that the memristor can be developed using a wide variety of materials and device structures. The reasons for the memristive effect include, but are not limited to, the motion of oxygen vacancies [1], the motion of silver dopants [7], and the state change in chalcogenide materials [9]. A complete study of which materials contain the required properties to be considered memristive has not yet been published. Until then, the reasoning for choosing each material in the devices appears to be on a case by case basis. Sung Hyun Jo and Wei Lu at the University of Michigan fabricated memristors published in [7] that are based on an amorphous silicon and silver. As voltage is applied, Ag ions are pulled into the a-si layer to lower the resistance of the device. The thickness of the a-si was 12nm and the cross-sectional area of the devices was 1 by 1nm. Sung Hyun Jo et al. also fabricated devices using a slightly different method in [8]. In this paper, a-si is co-sputtered with Ag at a ratio that changes as the layer is formed on the wafer. This produces a film that has a low concentration of Ag at one end and a higher concentration of Ag at the other. These devices have an area of 1 by 1nm. The devices had significantly lower switching times of about 5-1ns when compared to the device previously described in [7]. Antonio S. Oblea et al. has fabricated chalcogenide based devices where Ag 2 Se and Ag were placed between tungsten electrodes, [1]. Ge 2 Se 3 was placed between each layer to help the tungsten adhere, and to make it possible to deposit the Ag layer. The devices had a diameter of 18nm and were fabricated by first depositing a substrate, then 9

23 etching vias where the devices would be deposited. The electrodes were formed with a much larger area of 8 by 8µm. Nadine Gergel-Hackett et al. developed a flexible memristor that was deposited on a laserjet transparency [11]. The device is formed by letting a titanium isopropoxide solution hydrolyze to form a 6nm layer of amorphous TiO 2 placed between Al electrodes. The device is large with cross-sectional area of 4mm 2. The device shows on/off rations greater that 1,:1 and has data retention capabilities of about 14 days. This suggests that the memristive effect can be seen in devices with sizes that exceed the nanometer scale. A group led by T. Prodromakis conducted a study that tested memristance on devices that range from 1 by 1µm 2 to 2 by 2µm 2 to further show that the memristive effect is not only present in the nanoscale. The results show that hysteresis size and the ratio between the maximum and minimum resistance increase as the device area decreases [12]. Titanium dioxide memristors have also been fabricated using a slightly different approach; using a TiO 2+x layer in addition to the stoichiometric one. In this case, the abundance of oxygen atoms is negatively charged which theoretically creates a memristor with charges that move opposite to the TiO 2-x structure. T. Prodromakis et al. developed TiO 2 /TiO 2+x devices that exhibit memristive behavior with an active area of 1 to 25µm 2 [13] Spintronic Memristor Devices In addition to the development of thin-film memristors, attempts have been made to develop spintronic memristors [35-37]. The resistance is variable dependent on the 1

24 magnetoresistance and the spin torque induced magnetized motion. The device was designed using two ferromagnetic layers, one reference layer and one free. The free layer is split into two sections magnetized in opposite directions. The position of the barrier dividing the layers of opposite magnetization directions is what determines the resistance of the device. The advantage of this system is that it can be integrated into CMOS just as magnetic RAM that is currently commercialized. 2.3 RRAM RRAM is a device that works similarly to memristor devices, as it is a form of non-volatile memory that works by changing the resistance of a dielectric material. They are primarily made using an oxide layer between two electrodes. A common dielectric used in these devices is hafnium oxide where one example shows a device containing a 5nm HfO 2 layer [12]. The RRAM devices that have been fabricated generally have high and low resistance states that represent logic or 1, as opposed to memristors that could potentially hold many resistance states. 2.4 Device Modeling In addition to physical device development and characterization, memristor devices have also been modeled based on the equations first proposed by HP Labs [1, 14, and 15]. The memristor device was first modeled by two variable resistors in series. The resistance of each was determined by the instantaneous thickness of the two thin-film layers made up of high resistivity TiO 2 and low resistivity TiO 2-x. The thickness of the TiO 2-x layer is modeled using a state variable that changes based on the net charge 11

25 applied to the device. Some additional analysis was done in [14, 15] that expands on the equations presented by HP Labs in [1]. HP Labs released a memristor model in [1] that describes the charges in the doped layer to move with linear dopant drift. Since then, Joglekar and Wolf expanded on the model in [14] by defining a non-linear drift velocity. Furthermore, Zdenek Biolek et al. describe an alternative non-linear drift model for the memristor [15]. These models do not take into account the non-linear tunneling and heating effects described in [26, 27]. Further modeling has been completed based on the chalcogenide device developed at Boise State University [9, 39]. These models were developed so that the I-V characteristics of both the fabricated device and the model match very closely. The drawback of this type of model is that it conforms to the device data for a limited number of voltage inputs. 2.5 Circuit Design Circuit designs have been published that show how the memristor could be added to passive circuit theory using RLCM designs [14, 4]. This is an addition to RLC passive circuit theory that involves a non-linear, time-varying element. First and second order systems were developed as a memristor based approach to design chaotic oscillators. Circuits have also been published that use the memristor as a programmable resistor in an analog circuit [41]. Since high frequency signals with zero net flux do not disrupt the state of a memristor, a DC signal is applied to set the resistance value, and then the AC signal propagates with stable memristor operation. This technique has been 12

26 applied to programmable gain amplifiers, where the memristor is in place of the feedback resistor. Dr. Eshraghian et al. proposed a circuit design for a content addressable memory (CAM) cell that utilizes memristors [42]. For this design, the memristor is combined with CMOS transistors to provide a CAM cell with a 45% reduction in area when compared with an SRAM equivalent. This new MCAM cell also provides a 74% reduction in power consumption, although the write operation time is substantially longer due to the slow switching time of the memristor. Circuits have also been proposed that use memristors in cellular neural network (CNN) structures [2, 21]. The memristors act as synaptic weights, where the resistance represents signal strength. These circuits are based on a memristor/cmos hybrid design that would replace a transistor based design. A large number of read and write circuits were developed to control the information processing aspect of memristor devices. Some of these circuits involve using op amps as analog comparators that determine the state of a memristor [16-18]. To change the state of the memristor, a voltage pulse is applied where a transistor switching mechanism is used to control whether to read or write to the device. The read and write circuits proposed in [19] are complex designs that have the ability to modify the memristor resistance to a pre-defined set of 8 different values. 13

27 2.6 Applications The three most promising applications of the memristor are non-volatile memory [8, 16-19, 43], neuromorphic architectures [6, 7, 2, 21, 44, 45], and implication logic used for digital circuit design [46]. Non-volatile memory can be designed based on the dynamic resistance of the memristor device. For a simple one bit storage application, a high resistance could represent logic, and a low resistance could represent logic 1. Memristor based nonvolatile memory could potentially provide much more data storage per footprint area when compared the current technology [23]. Higher density can be achieved using the memristor as a multistate memory device [19]. Memristor based neuromorphic systems could be developed where the memristor holds a value representing the synaptic weight in a neural network [6]. Several papers have shown memristor fabrications where the memristor is capable of storing several different resistance values based on the application of a string of voltage pulses [6, 7, and 1]. Due to the dynamics of the memristor, logic design based on these devices is best done using material implication. A set containing the implication operator and the not operator, is computationally complete, as is the set {and, not}. The change in the logic operators is required as this would create a mathematical system that more closely resembles how memristors work [32]. 14

28 CHAPTER III PHYSICAL DEVICE EXPERIMENT 1 The following chapter discusses the fabrication and characterization of TiO 2 memristor devices. Of the all of the fabricated devices, the three most successful fabrications are known as UDMEM1, UDMEM2, and UDMEM8. The fabrication method of these devices is discussed, as well as the experimental setup and results obtained when testing the devices. 3.1 Device Fabrication UDMEM1, UDMEM2 and UDMEM8, differ in the thickness of the dielectric layers. UDMEM1 includes a 9 nm titanium oxide layer and a 44 nm oxygen deficient titanium oxide layer sandwiched between top and bottom electrodes (see Figures 3.1, 3.2, and 3.3). UDMEM2 has the same device structure except that the titanium dioxide layer was reduced to 45 nm and the TiO 2-x layer was reduced to 22 nm. UDMEM8 is a similar device with thinner titanium oxide layers (5 nm for titanium oxide and 5 nm for oxygen deficient layers). In each case, the bottom layer on the device is a 4 nm layer of Si with resistivity of 1 to 1 Ωcm. The titanium oxide layers were formed by magnetron sputtering at an oxygen pressure of 14 mtorr. The UDMEM1, UDMEM2, and UDMEM3 devices were formed at a temperature of 2 C, 35 C, and 4 C respectively. 15

29 For each of the devices, the bottom electrode was a typical metal stack used for Ohmic contact on low resistivity Si about 5 nm thick (Ti/Al/Ni/Au) capped with a 1 nm Pt layer. The top layer was a Ti/Au layer with a thickness of about 8 nm. The bottom metal layer was rapid thermal annealed at 85 C for 3 seconds to create the Ohmic contact to the Si substrate. Three wafers, one for each of the devices (UDMEM1, UDMEM2 and UDMEM8), were fabricated with several devices on each wafer. Metal 2 TiO 2-x TiO 2 Metal 1 Low Resistivity Si 8 nm 44 nm 9 nm 5 nm 4 nm Figure 3.1. Device layout for UDMEM1. Metal 2 TiO 2-x TiO 2 Metal 1 Low Resistivity Si 8 nm 22 nm 45 nm 5 nm 4 nm Figure 3.2. Device layout for UDMEM2. Metal 2 TiO 2-x TiO 2 Metal 1 Low Resistivity Si 8 nm 5 nm 5 nm 5 nm 4 nm Figure 3.3. Device layout for UDMEM8. Figure 3.4 (a) shows how multiple devices are aligned on the UDMEM2 wafer. Figure 3.4 (b) shows a single device being examined using a probe under a microscope. To test each device, a probe was applied to the top electrode, the 8 nm Ti/Au (see Figs. 16

30 1 and 2). The device was grounded through the low resistivity Si, which was connected to the bottom layer of the device. (a) (b) Figure 3.4. Memristors on wafer: (a) alignment of multiple memristors on a wafer, and (b) probe applied to test a single device. 3.2 Experimental Test Setup Two different methods were used to obtain the I-V curves for the devices. UDMEM1 and UDMEM2 were tested using a Keithley 24 SourceMeter, so that a voltage could be applied and the current read to generate device I-V curves. Each voltage was entered in step intervals by hand, first increasing to the maximum voltage, then decreasing past zero to the minimum voltage, and back to zero. This provides the ability to use a DC voltage source to apply voltage in a cyclic fashion. The UDMEM2 device was again tested along with UDMEM8 using a Princeton Applied Research computer controlled parameter analyzer in a cyclic voltammetry setup. UDMEM1 was not subject to further testing as it had inferior performance when compared to UDMEM2 in the initial testing. This method allowed many more points to be collected in a more accurate and efficient manner. The current for a number of voltage steps was recorded to obtain the resulting I-V plots. 17

31 3.3 Experimental Test Results The tests conducted on the fabricated memristors were done to first determine that the devices are acting as memristors, then to determine the extent to which these devices can successfully act as electrical synapses. First, tests were conducted to produce an I-V curve, both by hand and using a parameter analyzer. Then, repetitive pulses were applied to determine if this can effectively change the resistance of the device Characterization by User Controlled Test Setup The current-voltage results for UDMEM1 and UDMEM2 done using the Keithley SourceMeter are now examined to determine if the memristor device functions properly. First, a single device on each of the wafers was selected and a voltage loop was applied. In this test, a voltage loop is considered to be from V to 4V, then 4V to -4V, and back to V. Figure 3.5 shows the I-V curve for the UDMEM1 sample. A slight hysteresis loop can be seen where positive voltage was applied to the device. The current flowing through the device was slightly higher on the voltage decrease as opposed to the initial increase. Figure 3.6 shows the I-V results for the UDMEM2 sample. This sample had a thinner titanium dioxide layer, and had a larger hysteresis loop when comparing to the UDMEM1 sample. A small hysteresis can also be seen where the voltage is negative. The conductivity of UDMEM2 was slightly higher due to a thinner oxide layer. 18

32 Current ( A) Current ( A) Test 1: I-V UDMEM1 -.2V step -4:4V, SubTH=4um, A =.14cm 2 3 Voltage Increase 25 Voltage Decrease Voltage (V) Figure 3.5. Test results for UDMEM1 with a voltage loop ranging from -4V to 4V. Test 2: I-V UDMEM2 -.2V step -4:4V, SubTH=2um, A =.14cm2 7 Voltage Increase 6 Voltage Decrease 5 4 Figure 3.6. Test results for UDMEM2 with a voltage loop ranging from -4V to 4V. The UDMEM2 sample was then tested with an increased voltage range to see the changes in the hysteresis loop. The voltage loop was set from V to 5V, 5V to -8V, then - 8V to V. The upper limit on the voltage in this test was 5V because the meter used to determine current can only measure up to 15µA. At 5V, the current measurement was at a maximum so the voltage was then decreased. When the voltage was decreased, the current through the device peaked at -1.51µA. These results are plotted in Figure 3.7. It can be seen that the size of the hysteresis loop increased as voltage range tested became greater Voltage (V) 19

33 Current ( A) Test 3: I-V UDMEM2 -.5V step -8:5V, SubTH=2um, A =.14cm2 12 Voltage Increase 1 Voltage Decrease Voltage (V) Figure 3.7. I-V curve results for UDMEM2 with voltage ranging from -8V to 5V. The next test was designed to see how the hysteresis loop changed as multiple voltage loops were applied in succession. The UDMEM2 sample was selected for this test, as it provided the superior results when comparing the data in the previous plots. The voltage applied was increased from V to 5V, from 5V to -12V, then -12V to V. Since these tests were done on a different device on the UDMEM2 wafer, the results look different when comparing to the UDMEM2 test in Figure 3.7, especially when the voltage was negative. This device had a much higher current flow in the negative region as well as a larger hysteresis loop. This suggests that the wafer is not uniform, and different devices behave differently in different locations throughout the wafer. The following three plots show the I-V results when three consecutive voltage loops were applied to the device. Figure 3.8 shows the I-V curve for the first voltage loop, Figure 3.9 shows the second, and Figure 3.1 shows the third. 2

34 Current ( A) Current ( A) Current ( A) Test 4: I-V UDMEM2 -.5V step -12:5.5V, A =.14cm2 First Pass 12 Voltage Increase 1 Voltage Decrease Figure 3.8. Multiple voltage loop test, first pass Voltage (V) Test 4: I-V UDMEM2 -.5V step -12:5.5V, A =.14cm2 Second Pass 12 Voltage Increase 1 Voltage Decrease Figure 3.9. Multiple voltage loop test, second pass Voltage (V) Test 4: I-V UDMEM2 -.5V step -12:5.5V, A =.14cm2 Third Pass 12 Voltage Increase 1 Voltage Decrease Figure 3.1. Multiple voltage loop test, third pass Voltage (V) 21

35 When comparing Figures 3.8, 3.9, and 3.1, it can be seen that the hysteresis loop became less uniform as the second and third voltage loops were applied. The three I-V curves appeared to be most predictable when the voltage was positive. When the voltage was negative, the hysteresis changed much more between each pass and degraded more severely. This test clearly shows the hysteresis loop with an intersection when the current and voltage are both. This shows that the necessary conditions are met for this device to be considered memristive Characterization by Computer Controlled Test Setup After testing the devices using the Keithley setup, the computer controlled parameter analyzer was used to obtain further I-V results. First, a single device on the UDMEM2 wafer was selected and a voltage loop was applied similar to when using the Keithley SourceMeter. In this test, a voltage loop was considered to be from V to 5V, then 5V to -5V, and back to V. This loop was applied to the device five times and each pass was observed to see how the I-V curves changed. Figure 3.11 shows the I-V curve for the first pass on the UDMEM2 sample. A slight hysteresis loop can be seen when a positive voltage is applied to the device. Figure 3.12 shows the I-V curve for the second pass when testing the UDMEM2 sample. These results show that the size of the hysteresis loop increased when compared to the first pass. Then, the hysteresis started to degrade after the second pass, and the resulting I-V curve after the fifth pass can be seen in Figure In all three cases, the device was only conductive when positively biased. 22

36 Current ( A) Current ( A) Current ( A) 1 I-V Curve for UDMEM2 Pass Voltage (V) Figure Test results for UDMEM2 with a voltage from -5 to 5V on the first pass. 18 I-V Curve for UDMEM2 Pass Voltage (V) Figure Test results for UDMEM2 with a voltage from -5 to 5V on the second pass. 1 I-V Curve for UDMEM2 Pass Voltage (V) Figure Test results for UDMEM2 with a voltage from -5 to 5V on the fifth pass. 23

37 Current ( A) The test results for the UDMEM8 sample were similar to UDMEM2, except the hysteresis loop was slightly larger. Also, the device was more conductive since the titanium dioxide layers in this device were thinner than in the UDMEM2 sample. The initial increase in conductivity happened much faster in this sample when looking at the data for the first voltage loop pass in Figure Figure 3.15 shows how the size of the hysteresis loop increased during the second voltage pass. The fifth pass in Figure 3.16 shows degradation in the hysteresis much like in the UDMEM2 device. The UDMEM8 sample also shows that conductivity was only present when the device was positively biased. These tests both show the hysteresis loop with zero current at a zero voltage bias. 1 I-V Curve for UDMEM8 Pass Voltage (V) Figure Test results for UDMEM8 with a voltage from -4 to 4V on the first pass. 24

38 Current ( A) Current ( A) 12 I-V Curve for UDMEM8 Pass Voltage (V) Figure Test results for UDMEM8 with a voltage from -4 to 4V on the second pass. 12 I-V Curve for UDMEM8 Pass Voltage (V) Figure Test results for UDMEM8 with a voltage from -4 to 4V on the first pass Characterization Using Pulse Waveform The next test shows the UDMEM2 device s reaction to voltage pulses as opposed to a DC bias. Figure 3.17 shows the results when applying pulses to the device. This test was done by applying a 2% duty cycle pulse oscillating between and 4V to the memristor, with a frequency in the range of 3-5Hz. The number of pulses was determined by multiplying the frequency of the pulse waveform by the amount of time it was applied to the device. The source was applied for a set amount of time and then an Ohmmeter was used to measure the resistance across the device as the signal was turned 25

39 Change in Resistance (k ) off. This resistance was then compared to the resistance of the device before the source was applied to obtain the total resistance drop. This data supports the ultimate goal of having a memristor device model brain function, as the resistance was reduced with the application of pulse waveforms. Resistance Drop as a Function of the Number of Voltage Pulses Applied Number of Pulses Applied (t*f) Figure Test results showing the resistance drop across the memristor as a function of the number of voltage pulses applied to the device. 26

40 CHAPTER IV PHYSICAL DEVICE EXPERIMENT 2 A mask set has been developed to fabricate a more complex set of memristor devices. This mask set makes it possible to fabricate much smaller devices in terms of footprint area, as well as memristor crossbar arrays. The fabrication method for the second generation of devices is discussed, as well as the experimental test results for the first wafer fabrication using this new method. 4.1 Mask Design for Future Devices The second generation of memristor devices is based on a new mask set that makes it possible to fabricate devices that are isolated, as well as devices arranged in a crossbar pattern. The layout of the entire mask can be seen in Figure 4.1. The device area when using this mask is determined by the overlap between the top and bottom metal layers, and the overlap area ranges from µm 2 to 4 µm 2 for different the device patterns. 27

41 Figure 4.1. Layout of entire mask Overall Mask Set The mask set contains three different masks, the top metal, the bottom metal, and an etch mask. Figure 4.2 shows each mask it the mask set. It can be seen that all of the probing pads are present on the top metal mask, and only the pads connecting to the bottom electrode on the device are present on the bottom metal mask. The etch mask is used to provide access to the bottom metal, as vias will be etched wherever the pads connected to the bottom electrode need to be accessed from the top of the device. (a) Figure 4.2. Layout for (a) top metal mask, (b) etch mask, and (c) bottom metal mask. (b) (c) 28

42 4.1.2 Device Patterns in Mask Design Each mask is divided in to 4 different sections with an area of 1 cm 2, and 8 of each section are spread out over the entire mask. The four different sections of the mask are displayed in Figure 4.3. There are two different crossbar designs and two different sections of individual devices. Figure 4.3 (a) contains 9 different individual devices that range from 25µm 2 (rightmost device) to 4 µm 2 (leftmost device). Each of these device patterns resides between two larger patterns that will act as pads for the device to be probed. It can be seen that there are four rows of device patterns where each column represents a different device size. The pad above the device acts as the top electrode, and the pad below the device provides access to the bottom electrode. The actual memristor device is defined as a circular overlap between the top and bottom electrodes. This layout can be seen in more detail in Figure 4.4. The layout in Figure 4.3 (c) is a similar pattern, except that the devices are smaller in size and are defined by the overlap of two wires with a width of 5 µm as opposed to a circular overlap. The device size ranges from 2.5 µm 2 to 35 µm 2 with an additional device with zero overlap area. This was done to possibly examine the amount of fringe effects that are present in the devices fabricated using this mask design. The device level layout for the smaller devices can be seen in Figure 4.5. Figure 4.3 (b) shows one of the crossbar designs, the horizontal lines reside in the top metal mask, and the vertical lines represent the bottom metal. All of the larger pads are on the top metal mask so all the devices can be accessed using probes. The horizontal row of pads along the bottom are connected to the lower electrode as the etch mask is used to provide access. This will allow a voltage to be applied between one top wire and 29

43 one bottom wire to access any of the devices in the array. Each of the 36 devices at each of the cross-points is defined by a circle with an area of 1 µm 2. The layout in Figure 4.3 (d) is almost identical to the one in Figure 4.3 (c), except that there is no circle added and the devices are defined only by the crossing of the vertical and horizontal 5 µm wires for a device area of 25 µm 2. (a) (b) (c) Figure 4.3. Layout of 4 different areas in the mask set including (a) the larger individual devices, (b) the crossbar with 1 µm 2 overlap, (c) the smaller individual devices, and (d) the crossbar with 25 µm 2 overlap. 3 (d)

44 ... Figure 4.4. Span of devices that are included in the larger device set (25 µm 2 to 4 µm 2 ).... Figure 4.5. Span of devices in the smaller devices set ( µm 2 to 35 µm 2 ). 4.2 Second Generation Device Fabrication After the mask set was designed, it was used to fabricate a wafer for experimental testing. The device layout can be seen in Figure 4.6. A high resistivity SiO 2 film was deposited on a Si wafer so that the bottom electrode on each device would not short together. The Pt bottom metal was deposited using electron beam evaporation. Due to the high melting temperature of platinum, the process had to be completed in steps to prevent the heat radiated from the Pt target from destroying the wafer. Images of the wafer after Pt deposition can be seen in Figure 4.7. The TiO 2 and TiO 2-x layer were then deposited by sputter deposition using a Ti target with 6% O 2 in a 4mTorr Ar environment. The amount of DC power was varied to determine the composition of each oxide layer (23W for 31

45 TiO 2-x and 5W for TiO 2 ). The stoichiometric oxide layer was set to be much thinner than the oxygen deficient layer to create a device similar to the one described in [26]. An image of the wafer with the deposited oxide layers can be seen in Figure 4.8. The Pt top metal was applied to the wafer again using electron beam evaporation. The photoresist patterned for the top metal can be seen in Figure 4.9, and the completed wafer can be seen in Figure 4.1. Au 5Å Pt Ti TiO 2 5Å 5Å 4Å TiO 2-X 11Å Pt Ti 5Å 5Å SiO 2 1mm Figure 4.6. Device layout for second generation memristor device (contact pads not shown). (a) Figure 4.7. Images of the SiO 2 wafer after Pt deposition displaying (a) the contact pad and wire leading to an isolated device, and (b) the wire passing through the circular definition of a crossbar device. (b) 32

46 Figure 4.8. Image displaying memristor wafer after deposition of TiO 2 and TiO 2-x layers. (a) Figure 4.9. Images displaying the lithography pattern for the top metal for (a) an isolated device, and (b) a device in a crossbar. (b) (a) Figure 4.1. Images of fabricated wafer displaying (a) portion of a memristor crossbar, and (b) an array of single devices in a wire bonded packaging. (b) 33