High-speed logic integrated circuits with solutionprocessed self-assembled carbon nanotubes

Transcription

1 In the format provided by the authors and unedited. DOI: /NNANO High-speed logic integrated circuits with solutionprocessed self-assembled carbon nanotubes Shu-Jen Han*, Jianshi Tang, Bharat Kumar, Abram Falk, Damon Farmer, George Tulevski, Keith Jenkins, Ali Afzali, Satoshi Oida, John Ott, James Hannon, Wilfried Haensch Correspondence to: sjhan@us.ibm.com This file includes: Supplementary Figure S1 to S10 NATURE NANOTECHNOLOGY 1

2 Supplementary Figure S1. NFETs with and without sidewall passivation. a, SEM image shows the device with HSQ covering the channel region as well as contact regions with 40 nm gaps in between. These gaps define the final device contact length. b, SEM image shows the conventional contact scheme without sidewall passivation. NATURE NANOTECHNOLOGY 2

3 Supplementary Figure S2. The robustness of passivation for Sc/Au NFET contacts. a, Transfer curves from as-fabricated CNT NFETs with HSQ sidewall passivation and 20 nm Al 2 O 3 encapsulation layer. b, Transfer curves from the same set of devices in (a) measured after stored the chip in air for over 8 months. There is no performance drop and yield degradation that can be observed. 207 devices were measured at room temperature on a Cascade Microtech Summit semi-automated probe station NATURE NANOTECHNOLOGY 3

4 Supplementary Figure S3. Characteristics of bilayer gate dielectric consisting of 4 nm Al 2 O 3 / 3 nm HfO 2. a, Energy band diagram of Sc contact electrode, bilayer gate dielectric, and W gate electrode. Al 2 O 3 provides the high resistance to oxygen scanvenging effect seen in HfO 2 as well as a larger barrier between low-work function Sc and Al 2 O 3 compared to Sc and HfO 2, both help reduce the gate leakage. HfO 2 top layer is important in our current fabrication flow to provide larger process windows for processes such as RIE or wet etch. b, Gate current (I g ) as a function of gate bias (V g ) showing the robustness of bilayer gate dielectric above 3 V for both V g < 0 and V g > 0. The smaller gate bias window before high gate leakage when V g < 0 (left figure) reflects the fact that Sc has a lower work function than W gate (shown in (A)). NATURE NANOTECHNOLOGY 4

5 M11 S Supplementary Figure S4. UV-vis-NIR absorption spectra of the CNT solution after sorting. The spectra is of wavelength versus absorbance for the purified sample. The optical transitions corresponding to the semiconducting (S22) and metallic (M11) CNTs are labelled. As evidenced in the spectra, the M11 peak is completely attenuated while the S22 peak is strong. This implies that the purity is below the detection limits of the spectrometer. NATURE NANOTECHNOLOGY 5

6 Supplementary Figure S5. X-ray photoelectron spectroscopy (XPS) spectra of monolayer before and after diazotization. Black curve shows aniline hydroxamic acid monolayer that was self-assembled on the chip of HfO 2. After the diazotization process, the same chip was measured in XPS again (red curve) where the appearance of new N1S peak indicates the diazotization of aniline. The complete details of this method will be published elsewhere NATURE NANOTECHNOLOGY 6

7 Supplementary Figure S6. Transfer characteristics of PFETs and NFETs on the RO substrate. a, 192 PFETs (same data as in Figure 3c) with the subthreshold swing around 170 mv/decade with V th = 0.24V ± 0.17V. b, 192 NFETs with the subthreshold swing around 150 mv/decade with V th = 0.31V ± 0.24V. Both have the connected yield of 100%. V th is extracted based on a constant current of 10 na. Threshold voltage variability in CNT FETs V th variability affects both chip-level standby power as well as on-state current variation that determines the circuit speed. We have performed detailed study on this topic to understand the origin of large V th variability observed in typical CNT transistors, and summarized the study in our two previous publications 32,33. What we found is that, based on experimental data from various gate dielectric thicknesses and classic models, the dominant origin of V th variability in CNT FETs is from fixed charges distributed at the dielectric/passivation interface instead of any dopants absorbed on nanotubes 32. We constructed the standard Pelgrom plot using our experimental data and found that A(V th ) is about 4.5 mv μm for CNT FETs, comparable with that of 65 nm bulk Si technology. Furthermore, we built a microscopic Monte Carlo model to simulate carrier transmission in ballistic CNT FETs, and how discrete random fixed charges near the dielectric surface impacts V th variability 33. One interesting conclusion based on the simulation result is that, under certain low surface charge density, the scaling of channel length in ballistic CNT FETs can actually lead to improved V th variability, opposite to typical Si technologies. NATURE NANOTECHNOLOGY 7

8 Supplementary Figure S7. Transfer characteristics (V out vs. V in ) from 96 inverters. The dashed box indicates the 1 V bias window. Most of inverters were able to switch within this bias window. The plot also shows several inverters with weak NFETs, thus they could not switch to V ss (-0.5 V). The high yield along with tight variation control enable the high-performance ring oscillator running at low bias. NATURE NANOTECHNOLOGY 8

9 Supplementary Figure S8. Simulation of the RO stage delay as a function of CNT density with various assumptions. The red star indicates the measured stage delay from this work. The current circuit has an average of 5 CNTs per µm, sitting on the sharp portion of the curves, suggesting the speed is largely limited by parasitic capacitance. With reasonable process and material assumptions (a self-aligned structure to reduce overlap between gate and S/D down to 5 nm, increase tube density to 100 tubes/ µm, and reduce channel length to 10 nm while increase the drive current per tube to 3 µa), the stage delay can be reduced to sub-picosecond. It should be noted that the parasitic capacitance of the interconnect bridge between RO stage 1 and stage 5 is not included in the simulation. The size of the W bridge is 700 nm x 375 nm in the experiment. The calculated capacitance is around 3.1 ff. Using 5 tubes/µm per device with 30 nm L ov as an example, C g =0.06 ff and C ov =1.06 ff for each stage with the last stage having this additional interconnect bridge capacitance. Thus, this additional capacitance can introduce about 35% speed reduction. The will bring the projection closer to the experimental point. Note that in the final technology, this bridge capacitance should be significantly smaller with proper BEOL process (thicker interlayer dielectric with lower dielectric constant) NATURE NANOTECHNOLOGY 9

10 Supplementary Figure S9. CNT ring oscillator fabrication yield. a, SEM image of the fabricated array of CNT ring oscillators. The pad design matches the standard 25 pin probe card. b, Measured RO frequency at 2 V bias. A switch matrix was used to select which of the ring oscillators in the 25-pad design was being operated. Without the performance criteria, the yield of functional ROs is 55/160 = 34.3%. NATURE NANOTECHNOLOGY 10

11 Supplementary Figure S10.Explanation of non-rail-to-rail waveforms from measured CNT ring oscillators. The output of the ring oscillator is a buffer which is connected to the ring oscillator as a means to detect its frequency only. It is not intended to observe the internal voltage swing of the ring oscillator. The voltage swing of this output buffer is related to its size and the magnitude of the capacitive and resistive load of the measuring equipment and cable wiring (as much a 100 pf and/or 50 ohms). In a mature technology, the buffer is made of several stages of inverters, each with increasing size, with the final stage large enough to drive fairly large voltages. In our CNT ring oscillator, the output buffer was intentionally designed to be the same size as a stage of the ring oscillator. (This was because of concern that larger devices might not yield in this early CNT technology demonstration). Thus the voltage swing of the buffer is greatly reduced in rise time and amplitude, but is not in any way an indication that the ring oscillator itself does not swing to the supply voltage level. Just like in all logic circuit test, the purpose of the buffer is to isolate the actual circuit speed from the loading effect of measurement equipment. NATURE NANOTECHNOLOGY 11

12 Current density in CNT device on RO substrates We believe the lower current is attributed to: 1. Threshold voltage variation and selection and 2. Tube length variation among tubes within the device. In this demonstration, the threshold voltages for both NFETs and PFETs are not precisely controlled in terms of their location. The reduced overdrive from high threshold voltages in our devices can reduce the drive current. In addition, in this demonstration, we used side-bonded contact scheme (metal contact on the side of CNT), therefore the contact length (the actual contact area between CNT and metal) plays an important role in determining the current level. Since we did not apply CNT length selection process, for the trench occupied by a shorter CNT, the contact length can be shorter and affect the current. However, it should be noted that high current from individual CNT array device have been demonstrated recently 34, showing the promise of this technology. Our goal is to use this RO platform as the future CNT process development vehicle. Once the unit process becomes mature, we will adopt and incorporate into RO. For example, further improved passivation (to reduce device Vt variation), threshold voltage control (by doping or gate workfunction), and end-bonded contact scheme are essential to continue to push the RO performance References Cao, Q., Tersoff, J., Han, S. J. & Penumatcha, A. Scaling of device variability and subthreshold swing in ballistic carbon nanotube transistors. Physical Review Applied 4, (2015). Cao, Q. et al. Origins and characteristics of the threshold voltage variability of quasiballistic single-walled carbon nanotube field-effect transistors. ACS nano 9, (2015). Brady, G. J. et al. Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs. Science Advances 2, e (2016). NATURE NANOTECHNOLOGY 12