Stanford University. Virtual-Source Carbon Nanotube Field-Effect Transistors Model. Quick User Guide

Transcription

1 Stanford University Virtual-Source Carbon Nanotube Field-Effect Transistors Model Version Quick User Guide Copyright The Board Trustees of the Leland Stanford Junior University 2015 Chi-Shuen Lee and H.-S. Philip Wong Dept. of Electrical Engineering, Stanford University All rights reserved. 1

2 Acknowledgement The developers would like to thank Prof. Zhihong Chen (Purdue), Prof. Aaron Franklin (Duke), Dr. Wilfried Haensch (IBM) for the use of the CNFET experimental data and useful discussion; Prof. Lan Wei (Waterloo), Prof. Shaloo Rakheja (NYU) for the useful discussion on the virtual source model; and Prof. Eric Pop, Gage Hills, and Prof. Subhasish Mitra at Stanford University for valuable assistance in identifying the desirable modifications and testing of the model. This work is supported in part through the NCN-NEEDS program, which is funded by the National Science Foundation, contract EEC, and by the Semiconductor Research Corporation, and through Systems on Nanoscale Information fabrics (SONIC), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA, the member companies of the Initiative for Nanoscale Materials and Processes (INMP) at Stanford University, as well as IBM through the Center for Integrated Systems (CIS) at Stanford University. 2

3 I. Introduction The Stanford Virtual-Source Carbon Nanotube Field-Effect Transistor model (VS-CNFET) is a semi-empirical model that describes the current-voltage (I-V) and capacitance-voltage (C-V) characteristics in a short-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with carbon nanotubes as the channel material. The model captures dimensional scaling properties and includes parasitic resistance (CNT-metal contact and doped extensions), parasitic capacitance (mate-to-metal coupling capacitance and metal-cnt fringe capacitance), and tunneling leakage currents (direct source-to-drain tunneling and gate-to-drain junction band-to-band tunneling). The intrinsic drain current and terminal charges are calculated based on the virtual source (VS) concept [1-2]. This work aims to provide a predictive model that captures the essential physics of CNTs and reflects the experimental observation, while preserving computational efficiency so that circuitlevel simulation, and system-level performance assessment can be carried out effectively. Therefore, some equations are empirical but not completely physical. Calibration of the model is performed at room temperature, i.e. T = 25 C. For temperatures other than 25 C, some empirical parameters in the model need to be re-calibrated to experiments or rigorous numerical simulations, and the correctness is not guaranteed. The VS-CNFET is only applicable to MOSFET-like CNFETs but not applicable to Schottkybarrier type CNFETs. Furthermore, the CNTs are assumed to be all semiconducting. This quick user guide introduces the basic concept of the VS-CNFET model and provides operational guidance. Users can refer to the Stanford VSCNFET Technical User s Manual and [3][4] for detailed physics and discussion. II. Package Files File/Directory Name vscnfet_1_0_0.va vscnfet_1_0_0_verilog_test_bench vscnfet_1_0_0_matlab_exerciser vscnfet_1_0_0_experimental_data vscnfet_1_0_0_manual.pdf vscnfet_1_0_0_qug.pdf parameter_set.txt Description VSCNFET model in Verilog-A Example HSPICE files for model use demonstration Model and demonstration files in Matlab Experimental I-V data used for calibration Technical user s manual (technical details) Quick user guide (operational guidance) A set of default input parameters, which has already been coded in vscnfet_1_0_0.va III. Model Parameters and Scope CNFET Device Structure 3

4 A representative CNFET structure modeled in the VS-CNFET is shown in Fig. 1a: a cylindrical gate-all-around structure with heavily doped source/drain extensions. The CNTs sit on a thick insulator (e.g. SiO2) so the body terminal is assumed to have no effects. As a result the VS-CNFET is a three terminal transistor model. P-type CNFETs are completely symmetric with n-type CNFETs, i.e. characteristics of I-V and C-V are the same for p-cnfets and n-cnfets given the same Vgs and Vds. Fig. 1. (a) A representative gate-all-around CNFET structure used in the VS-CNFET model with the dimensions, User-Defined Input Parameters Inputs to the VS-CNFET are design-related parameters such as the gate length (Lg), contact length (Lc), CNT diameters (d), and gate oxide thickness (tox), as listed in Table I. The column suggested scope shows the range of the input that has been tested. Any values outside the suggested scope may lead to unexpected results, though the model may still generate outputs as long as the given inputs are valid. Table I. VS-CNFET Input Parameters Name Suggested Scope Description type -1 or 1 type of transistor. 1: nfet; -1: pfet s [2.5e-9:inf) spacing between the CNTs (center-to-center) [m] W [s:inf) transistor width [m] Lg [5e-9:100e-9] physical gate length [m] Lc [1e-9:inf) contact length [m] Lext (0:inf) source/drain extension length [m] (or spacer length) 4

5 d [1e-9:2e-9] CNT diameter [m] tox [1e-9:10e-9] gate oxide thickness [m] kox [4:25] gate oxide dielectric constant kcnt 1 CNT dielectric constant ksub [1:kox) substrate dielectric constant kspa [1:16) source/drain spacer dielectric constant Hg [0:inf) gate height [m] Efsd [-0.1:0.5] Fermi level to the band edge [ev] at the source/drain, related to the doping density. The larger the Efsd, the higher the doping density in the source/drain extensions. Vfb [-1:1] flat band voltage [V] (for threshold voltage adjustment) Geomod 1 or 2 or 3 device geometry. 1: cylindrical gate-all-around; 2: top-gate with charge screening effect; 3: top-gate without charge screening effect Rcmod 0 or 1 or 2 contact mode. 0: user-defined value, Rs0; 1: diameter-dependent transmission line model; 2: diameter-independent transmission line model (Rc is calculated at d = 1.2 nm regardless of the input d) Rs0 [0:inf) User-defined series resistance (Ω) SDTmod 0 or 1 or 2 source-to-drain tunneling (SDT) mode. 0: SDT inactivated 1: SDT with inter-band tunneling 2: SDT without inter-band tunneling BTBTmod 0 or 1 band-to-band tunneling mode. 0: off; 1: on *temp 25 Temperature ( C) *The temperature is an internal variable in Verilog-A and can be specified in the SPICE netlist. The user should note that the VS-CNFET v1.0.1 are calibrated only at room temperature (i.e. 25 C). Any temperature other than that may lead to unexpected results. IV. Model Output Dependency The VS-CNFET model takes the device structure as inputs (see Table I) and calculate the intrinsic device-level parameters and parasitic effects. This section describes the first-order dependency of the output current and capacitance on the device design parameters listed in Table I. Users can refer to the Technical User s Manual for detailed equations. Intrinsic I-V and C-V The intrinsic drive current is a function of W ( ) 1, Lg ( ), s ( ), d ( ), and gate capacitance ( ). 1 stands for positive correlation, while stands for negative correlation 5

6 The gate capacitance is a function of biases and depends on tox ( ), kox ( ), d ( ), and Geomod. The subthreshold I-V relation is characterized by the inverse subthreshold slope (SS), draininduced barrier lowering (DIBL), and threshold voltage (VT). As Lg decreases, SS and DIBL both increase, and VT decreases. In addition, VT is directly proportional to Vfb. SS, DIBL, and VT also depend on tox, kox, and d due to the different resulting electrostatic control. Parasitics The parasitic contact resistance is a function of d ( ) and Lc ( ). The parasitic extension resistance is a function of d ( ), Efsd ( ), and Lext ( ). The parasitic capacitance is a function of kspa ( ), Hg ( ), and Lext ( ). Tunneling leakage Currents The direct source-to-drain tunneling current (ISDT) is a function of d ( ), Lg ( ), kspa ( ), and Efsd ( ). It also depends on tox and kox but not significantly. Note that ISDT can be turned off by setting SDTmod = 0; SDTmod = 1 turns on ISDT; and SDTmod = 2 turns on ISDT without inter-band tunneling (see Section V for more details). The band-to-band tunneling current (IBTBT) is a function of d ( ), kspa ( ), and Vds ( ).IBTBT can be turned off by setting BTBTmod = 0. 6

7 V. CNFET Device and Circuit Simulation In this section, I-V and C-V characteristics of a representative CNFET as well as simple circuit simulations are demonstrated. Table II summarizes the model inputs, corresponding to a projected contacted gate pitch equal to 31 nm at the 5-nm technology node [3]. Vfb and Efsd are selected such that Ioff = 100 na/μm and nsd = 10 9 /m; p-type CNFETs are assumed to be completely symmetric with n-type CNFETs; finally, supply voltage Vdd = 0.71 V is used throughout this section. All the simulation scripts can be found in the folders vscnfet_1_0_0_verilog_test_bench and vscnfet_1_0_0_exerciser, where users can also find the VS-CNFET model implemented in MATLAB and Verilog-A. The simulation environments are MATLAB (R2010a) for the MATLAB model, and HSPICE H SP2 64-BIT for the Verilog-A model. Table II. Input Parameters for Demonstration Input Value type 1 s 10 nm W 1 μm Lg 11.7 nm Lc 12.9 nm Lext 3.2 nm d 1.2 nm tox 3 nm kox 23 kcnt 1 ksub 3.9 kspa 7.5 Hg 20 nm Efsd Vfb Geomod 1 Rcmod 1 Rs0 3.3e3 SDTmod 1 BTBTmod 1 temp 25 7

8 A. Current-Voltage Characteristics As shown in Fig. 18a, Id increases as Vgs becomes very negative due to the increase in interband direct source-to-drain tunneling current. As discussed in Section II.E.1, the potential profile modeled in the calculation of ISDT in the version does not consider the gradual potential tails in the source/drain extensions (see the green line in Fig. 11). As a result, the modeled ISDT is larger than the numerically simulated result in the deep subthreshold region with SDTmod = 1. Users can set the input SDTmod = 2 to artificially turn off the inter-band SDT as demonstrated in Fig. 18a as the dashed lines. Fig. 18. Demonstration of I d-v gs characteristics with the inputs defined in Table II. The dashed lines represents the I d with the inter-band direct source-to-drain tunneling being turned off by setting SDTmod = 2. Fig. 19. (a) Demonstration of I d-v ds characteristics with inputs defined in Table II. 8

9 Fig. 20. Transconductance (a)(c) g m = di d/dv gs (b)(d) g ds = di d/dv ds. (a) and (b) are generated with Rcmod = 1, while (c) and (d) are generated using Rcmod = 0 and Rs0 = 3.3e3. 9

10 B. Capacitance-Voltage Characteristics We define the total small-signal gate capacitances as follows: / / C L C 2 C / W GG g gg par C L C C W GS g gsi par C L C C W GS g gsi par (55) where Cgg, Cgsi, and Cgdi are defined in (52). The C-V characteristics with inputs defined in Table II are demonstrated in Fig. 21. Fig. 21. Demonstration of C-V characteristics with inputs defined in Table II. (a) C-V gs at V ds = (b) C-V ds at V gs = V dd. Parasitic capacitance is dominant in this case. C. Inverter Transfer Curve Fig. 22. Demonstration of transfer curve of an inverter. 10

11 D. Fan-Out-4 Inverter Chain Fig. 23. Demonstration of transient analysis of a fan-out-4 inverter chain. The average of rising and falling delay is 13.9 ps. E. Fan-Out-1 9-Stage Inverter Ring Oscillator Fig. 24. Demonstration of transient analysis of a FO1 9-stage inverter ring oscillator. The period is 91.9 ps. 11

12 Reference [1] A. Khakifirooz, O. M. Nayfeh, and D. Antoniadis, A Simple Semi-empirical Short-Channel MOSFET Current Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters, IEEE Trans. Electron Devices, vol. 56, no. 8, pp , Aug [2] S. Rakheja and D. Antoniadis (2013), MVS Nanotransistor Model (Silicon), [3] C.-S. Lee, E. Pop, A. Franklin, W. Haensch, and H.-S. P. Wong, A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime Part I: Intrinsic Elements, IEEE Trans. Electron Devices, 2015 (in preparation). [4] C.-S. Lee, E. Pop, A. Franklin, W. Haensch, and H.-S. P. Wong, A Compact Virtual-Source Model for Carbon Nanotube Field-Effect Transistors in the Sub-10-nm Regime Part II: Extrinsic Elements, Performance Assessment, and Design Optimization, IEEE Trans. Electron Devices., 2015 (in preparation). 12