3-D Modelling of the Novel Nanoscale Screen-Grid Field Effect Transistor (SGFET)

Transcription

1 3-D Modelling of the Novel Nanoscale Screen-Grid Field Effect Transistor (SGFET) Pei W. Ding, Kristel Fobelets Department of Electrical Engineering, Imperial College London, U.K. J. E. Velazquez-Perez Departamento de Fisica Aplicada, Universidad de Salamanca, Spain

2 Outline Objectives/Motivation Proposed SGFET Structure Simulation Results Proposed Fabrication Steps Conclusions

3 Objectives To propose a novel 3-dimensional FET structure which overcomes the fundamental limitations of sub-micron FETs for future device scaling. Current Requirements: High Operation Speed High packing density Low power consumption Short channel effects: Source: Logic Technology Development, Intel Corporation High electric field High leakage current High power consumption Source Gate Drain SiO 2 FinFET

4 Proposed Structure SGFET: a novel approach to 3-D gating Source contact Drain contact Gate Contact Gate Electrode 3-D view cross section Si Device Layer Buried SiO 2 Layer Si Substrate Layer Deposited Insulator Layer S Gate Electrodes D Si Channel Thermal SiO 2 (Gate Oxide) Buried oxide D G S D S Thermal oxide Silicon channel SiO 2 Si substrate Contact Silicon substrate Side view cross section Top view cross section Current flow

5 Proposed Structure Why SGFET? SG Screen Grid principle from vacuum tube technology Plate Plate Grid Filament Cathode Control Grid Filament Screen Grid Cathode To reduce the capacitance and act as electrostatic shield between the control grid and the anode Triode Tetrode SGFET: Screen-Grid refers to the extra row of gate cyclinders that we add in to screen the effect of drain-induced barrier lowering, DIBL

6 Proposed Structure Gating Effect: Conventional MOSFET gating SGFET gating Side View Side View Top View Top View Gate Electrode Gate/Field Oxide Si Channel Depletion region Buried oxide Current flow Gating action Gating action

7 3-D Simulations SGFET: TAURUS TM Simulation Source Gate contact Cylindrical gate electrodes Field oxide Drain Simulation Structure Gate diameter Channel L inter distance Si channel Buried oxide Channel width Source n-doped cm -3 L g distance Drain n-doped cm -3 Si substrate 0.2µm S-D distance Gate oxide 0.2µm 3-D view Top cross-sectional view General dimensions: Si channel thickness=40nm. buried oxide thickness=460nm. field oxide thickness=300nm Lg=130nm. Linter=300nm. S-D distance=600nm. gate diameter=100nm gate oxide thickness = 10nm. source and drain regions doping density=1 x cm -3 (n-type)

8 3-D Simulation Results Influence of Channel Width W3 W2 W1 Silicon channel 1) Linear operation region V DS = 0.05V Row 1 Row 2 Cylindrical gate electrodes I V GS = 0V (A) I DS (A/µm) V T (V) S (mv/decade) Single W x x Double W x x Triple W x x ) Saturated operation region V DS = 3.00V I V GS = 0V (A) I DS (A/µm) V T (V) S (mv/decade) Single W x x Double W x x Triple W x x

9 3-D Simulation Results Influence of Geometrical Structure (Number of Rows/Arrangement) S D S D S D S D Drain Current (A/um) 1.2E E E E E E-06 1 row 1 row (source) 1 row (drain) 2 rows 0.0E Drain Voltage (V)

10 3-D Simulation Results Influence on DIBL reduction (Threshold Voltage Shift) S-D distance (nm) Number of rows 2 rows 1 row 2 rows 1 row 2 rows 1 row V T / V D (mv/v) Row 2 acts as screen grid to DIBL effect! SGFET

11 Simulated depletion region V D =0.05V, V G =0V to -1V 3-D Simulation Results

12 Simulated depletion region V D =0.05V, V G =0V to -1V 3-D Simulation Results

13 3-D Simulation Results Simulated electron concentrations 1) V G =0V V D =0.05V 2) V G =-0.3V V D =0.05V 3) V G =-0.5V V D =0.05V 4) V G =-1.0V V D =0.05V

14 3-D Simulation Results Influence of Channel Doping Concentration Drain Current (A/um) 1.E-05 1.E-06 1.E-07 1.E-08 Subthreshold slope improves at lower doping density 1.E-09 11e14 x cm-3 11e15 x cm-3 1.E-10 11e16 x cm-3 11e17 x cm-3 55e17 x 10 cm-3 1.E-11 88e17 x 10 cm-3 11e18 x cm-3 1.E Gate Voltage (V) S/D doping density 1x10 19 cm -3 Channel Doping Density

15 3-D Simulation Results Threshold voltage variation by variation in gate work function 0.8 Threshold Voltage (V) Gate Work Function (ev) -0.6

16 3-D Simulation Results Comparison Study between SGFET, bulk MOSFET, SOI MOSFET G D S D G S D G S Si Si SiO SiO 2 2 Si Si Si SGFET Bulk MOSFET SOI MOSFET General dimensions for all devices: S-D distance 60nm/600nm gate oxide thickness 5nm channel doping density 1x10 14 cm -3 channel width 50nm S/D doping density 1x10 17 cm -3 SOI wafer 40nm Si channel thickness

17 3-D Simulation Results Comparison Study between SGFET, bulk MOSFET, SOI MOSFET 1.E-04 Sub-threshold slope g m / I D 40 Drain Current (A/um) 1.E-06 1.E-08 1.E-10 1.E-12 1.E-14 S-D 600nm S-D 60nm Transconductance-Drain Current Ratio (1/V) 1.E Gate Voltage (V) Gate Voltage (V) SGFET Good Sub-threshold Characteristic High Transconductance Efficiency SGFET Bulk MOSFET X SOI MOSFET

18 Planned Fabrication Steps START Start with SOI wafer Define active region Source and drain implantation Define field insulator Define gate region Gate oxide growth Gate metalisation Pattern gate contact Define ohmic contact END Pattern S/D contact

19 Conclusions 2nd row gate fingers act as screen-grid to reduce DIBL effect. SGFET works well with channel at low doping levels - without loss in carrier mobility. Reduction in device length does not drastically degrade device s performances compared to SOI or bulk MOSFET. Therefore SGFET offers the possibility of downscaling without degrading the output characteristic.

20 Electron concentration plot for n + n - junction Vg=0V Vg=-0.6V Depletion Region (½ of background doping)