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1 4: Transistors Non idealities

2 Inversion Major cause of non-idealities/complexities: Who controls channel (and how)?

3 Large Body(Substrate) Source Voltage V G V SB n+ n Increasing Vsb Makes source/bulk More reverse biased V G n+ n V SB Increases depletion Region (and reduces free carriers even more) More potential needed at gate to invert channel => Threshold increases

4 Small Body(Substrate) Source Voltage V G V SB V SB n+ n V G n+ n Reducing Vsb Makes source/bulk less reverse biased Reduces depletion region (and increases free carriers even more) Less potential needed at gate to invert channel => Threshold Reduces

5 Threshold voltage body-bias dependance V T =V T0 V SB s s = t ox ox 2 N A q s Body effect coefficient reduces with technology scaling (tox reduces with scaling, NA increases but not that much)

6 Circuit implications of body effect This transistor has higher threshold. This node rises above 0V and reverse Biases SB. Body of all NMOS Usually tied to ground Body of all PMOS Usually tied to VDD High threshold not good For Speed. But good for leakage reduction!

7 Adaptive Body Bias Technique VBP VBP generator VBN VBN generator Controller Speed Target Leakage Target Process Monitor

8 Mobility degradation V SB n+ n Vertical electric field attracts free carriers. Collision at channel/oxide interfaces slows them down.

9 Velocity Saturation E c ~ 0.3V/um (for nmos) and 1V/um (for pmos)

10 Effect on I-V (I = Q/transit time = Q * velocity/l)

11 α power model

12 Channel Length Modulation L eff L eff n n n+ - n In saturation, Pinchoff region length increases with increasing VDS This reduces effective channel length I DS = / 2 V GS V T 1 V DS is technology dependent parameter (different for NMOS and PMOS)

13 Channel Length Modulation I DS Slope = λ V DSsat V DS Impacts Analog circuit design more than digital designs Gain is reduced

14 Short Channel Effect For small channel length devices Source and drain depletion regions penetrates channel As a result, channel is partially depleted Hence less gate voltage needed to invert the channel V T reduces 14

15 Greater control of gate => lower V T 15 Narrow Width Effect V T Narrow width effect For LOCOS gates, Reverse Narrow width effect Extra depletion region under bird's beak needs to be inverted => increases V T For STI, fringing fields helps in channel inversion W

16 Drain Induced Barrier Lowering Energy band bends due to applied drain bias Enhances minority carriers => reduction of threshold voltage Enhances Subthreshold current as a function of Vds Modeled as (where η = DIBL coefficient) V T =V T0 V SB V DS 16

17 Circuit implications 17 Park the Vds of off transistors close to 0V to reduce leakage

18 Halo Implant 18 p+ p+ Reduce impact of high drain fields to improve DIBL But...

19 Reverse Short Channel Effect 19 Reverse short channel effect p+ p+ V T increases as channel length is reduced

20 Circuit Implications Large L used for reduced leakage (except when you have RSCE) Small increases in W from minimum size doesn't help when you Have RNWE 20

21 Temperature Effects Reducing mobility Reducing V T (and more carriers) T = T r T k T r k= V T T =V T T r b T T r b = 0.5mV/K...3mV/K

22 Subthreshold current with temperature log I DS Subthreshold slope degrades (increases) Increasing temperature HW1.1: Find ratio of I DS (T=125C)to I DS (T R = 25C). assume: n = 1.56, large V DS, V GS = 0 b = 2mV/K, k = 2, V(T R ) = 200mV V GS

23 23 GIDL: Gate Induced Drain Leakage Severe when Vg is much lower than Vd Example: Inverter with input 0. Inversion when gate is sufficiently lower than drain! n+ n+ Halo implant makes it worse Ec Band to Band tunneling Ev

24 Circuit implication of GIDL 24 Using negative gate voltage helps to reduce subthreshold leakage But will increase GIDL.

25 Gate Leakage 25 Thin gate oxide (a few 10s of angstroms) Charge tunnels across the oxide barrier Stronger in NMOS than PMOS due to difference in barrier heights. Difficult problem to deal with: Need device solution

26 Gate Leakage

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