CMOS Scaling and Variability

Transcription

1 WIMNACT WS & IEEE EDS Mini-colloquim on Nano-CMOS Technology January 3, 212, TITECH, Japan CMOS Scaling and Variability NEC Tohru Mogami WIMNACT WS 212, January 3, Titech 1

2 Acknowledgements I would like to thank members of Robust program in MIRAI project for supporting data, and especially Dr. A. Nishida for discussing a lot of issues. This work is supported by NEDO. WIMNACT WS 212, January 3, Titech 2

3 Outline 1. CMOS scaling and Variation 2. Evaluation methods of Variation 3. How to improve variation? 4. Summary WIMNACT WS 212, January 3, Titech 3

4 CMOS scaling and Breakthrough technologies LDD structure Salicide Dual gate SDE, Halo T. Eimori, SFJ26 Modified by A.N. Oxide Nitridation Lg=1.mm Relaxation of Electric field Need new device & new process Lg=.5mm Reduction of resistance Scaling Compensate of Device variation Lg=.25mm Lg=.18mm Performance of PMOS Variability Issue Local stress HK/MG 4-6nm High Mobility Lg=.13mm Low gate leakage Plasma Nitridation 7-9nm High Quality of Gate Oxide <1nm New structures New materials 1-15nm Planer/3D CMOS w/ HK/MG 2-3nm WIMNACT WS 212, January 3, Titech 4

5 Vth variation on chip and on Wafer Vth distribution in wafer Vth X CY CY1 CX1 Systematic variation on wafer CX2 CX CX3 CX4 Vth mapping CY3 系列 系列 系列111 系列89 系列67 系列 系列 系列 Systematic & Random variation on chip CY CY2 系列111 系列89 系列67 系列 E-4 1.E-5 1.E-4 1.E-7 1.E-5 1.E-8 1.E-6 1.E-9 Ids [A] 1.E E E-8.8 Vg [V] E-6 1.E-9 1.E E-4 1.E-7 1M DMA-TEG on chip 1.E-5.61.E-8.8 Vg [V] E-6 1.E-9 Ids [A] 1.E-4 1.E-7 Ids [A] Ids [A] 1.E-6 1.E-1 Subthreshold characteristics of 2 devices on each chip E E-8.8 Vg [V] 1.E-9 1.E Vd=1.2 V WIMNACT WS 212, January 3, Titech Vg [V] 1.2 5

6 Normal Distribution Count [a.u.] Vth random variation of N/P-FETs Normal Distribution σ For 1M devices, Vth variation shows normal distribution. For 256M, Vth variation of NFET shows normal, but that of PFET shows normal and tail distribution V th [V] 2 NMOS Normal Distribution -3 NMOS PMOS -2-4 PMOS V th Vthc [V] (a) Vth variation for 1M devices V th (V) V th [V] (b) Vth variation for 256M devices WIMNACT WS 212, January 3, Titech 6

7 Standard deviation Physical parameter L W Tox Nsub Physical parameter vs. Vth variation What is the relationship between physical parameters of MOSFET and Vth variation? Theoretical threshold voltage and its standard deviation Threshold qnsubwdep Vt VFB S voltage C Vt q C inv N sub W 3LW dep : Gate length : Gate width : Gate oxide thickness : impurity in Si substrate etc. L, W scaling Enhance of variation by (LW). inv WIMNACT WS 212, January 3, Titech 7

8 Variation mechanisms 7nm Random variation can come from several origins. RDF and LER are the main origins of the random variation. 1 Random Dopant Fluctuation (RDF) Depend on channel dopant fluctuation Dopant fluctuation Potencial distribution 3 Oxide Thickness Fluctuation (OTF) Depend on gate insulator variation S D channel 2 Line Edge Roughness (LER) 4 Local grain depletion of gate (LGD) Depend on local variation of gate length Depend on local grain-depletion 7nm WIMNACT WS 212, January 3, Titech 8

9 Vth Random Variation & Pelgrom Plot Dr. Pelgrom proposed and demonstrated the simple evaluation method of the random variation in This is based on the simple statistics and useful. VTH A VT LW A t VT INV N SUB W DEP M. J. M. Pelgrom et al., IEEE JSSC, vol. WIMNACT WS 212, January 3, 24, Titech p. 1433,

10 Vth variation prospect Pelgrom plot can foretell the simple prospect of Vth variation. Simple device scaling-down can happen large Vth variation. If Avt keeps 3.8, 7nm FET will have about 4mV in Vth variation. Device parameter optimization, such as Tinv and gate work function, can improve the variation. If we need <1mV in Vth variation at 7nm FET, Avt should be 1.. Need the new technology of variation improvement for the future generation. Vth [V] Tox=2nm 32nm 65nm 25 15nm 5 Avt=3.8 1/(LW).5 [um -1 ] Avt=2. 7nm Avt= WIMNACT WS 212, January 3, Titech 1

11 Outline 1. CMOS scaling and Variation 2. Evaluation methods of Variation 3. How to improve variation? 4. Summary WIMNACT WS 212, January 3, Titech 11

12 Pelgrom Plot Pelgrom plot has been a simple and useful method to evaluate the random variation. Is there any issue of Pelgrom plot? Is variation of 25nm MOSFET really smaller than that of 5nm MOSFET? WIMNACT WS 212, January 3, Titech 12

13 Issue of Pelgrom Plot V TH Standard Deviation (mv) Pelgrom plot is very useful when the data come from the devices with the same Tox and Vth. It can make variation date into a straight line. However, for the devices with the different Tox and Vth, pelgrom plot cannot make those into a straight line. 12 WIMNACT WS 212, January 3, Titech 8 4 High N SUB Large T OX Pelgrom Plot Slope: A VT Device with the same LW 1 2 1/(LW) 1/2 (mm 1 ) Low N SUB Small T OX K. Takeuchi et al. Silicon Nano. Workshop, p.7, 27. K. Takeuchi et al. IEDM, p. 467,

14 VTH q C q 3 INV OX T NSUBW 3LW INV New normalization method New normalization method has been proposed by Dr. K. Takeuchi. This can handle the variation data for devices with and w/o different Nsub and Tox. ( V TH DEP V LW FB 2 ) F V TH V qnsubw CINV FB DEP 2 V Determined by Impurities +.1V F TH qn C SUB W INV DEP V FB 2 F VTH. 1.1V for poly-si gate. It varies in metal gate VTH B VT Where, T B INV VT ( VTH VFB 2 F ) LW q 3 OX K. Takeuchi et al. Silicon Nano. Workshop, p.7, 27. K. Takeuchi et al. IEDM, p. 467, 27. WIMNACT WS 212, January 3, Titech 14

15 V th [mv] Takeuchi Plot V th [mv] Pelgrom plot can handle variation data for devices with the same Vth and Tox. Takeuchi plot can handle both data and make them into a line if the process is the same. HV th MV th LV th Pelgrom plot T ox =4nm T ox = 3nm HV th MV th LV th Takeuchi plot T ox =4nm T ox =3nm T ox =2nm 2 1 T ox =2nm / LW [um -1 ] T INV (V th +.1)/LW [nm.5 V.5 um -1 ] WIMNACT WS 212, January 3, Titech 15

16 Vth Random Variation.35um-65nm devices have been analyzed by Takeuchi Plot, which can normalize L, W, Vth, and Tox. Vth variation of NFET was larger than that of PFET for every generation. PMOS random variation is determined by RDF. Origins of NMOS random variation are RDF and others. 8.35mm Process Technology 9nm 65n m 8.35mm Line-A Process Technology 9nm 65nm Line-D Robust A VT or B VT 6 4 Line-A Line-B Line-C Line-D Line-E Robust A VT or B VT 6 4 x 1.5 Line-B Line-C Line-E A VT 2 A VT 2 B VT Dopant fluctuation (flat doping) P-channel transistors B VT WIMNACT WS 212, January 3, Titech Dopant fluctuation (flat doping) N-channel transistors 16

17 Outline 1. CMOS scaling and Variation 2. Evaluation methods of Variation 3. How to improve variation? 4. Summary WIMNACT WS 212, January 3, Titech 17

18 Variation difference Takeuchi plot has revealed that Vth variation of NFET was larger than that of PFET for every generation. Only NFET with channel Boron showed reverse short channel characteristics. This indicated that channel Boron can be segregated near the junction edge. WIMNACT WS 212, January 3, Titech 18

19 Enhanced Variation mechanism Boron transient enhanced diffusion (TED) can be the origin of reverse short channel effect and the larger Vth variation of NFET. After As I/I for S/D region, interstitial Si (I-Si) has randomly produced near S/D region. During S/D annealing, B makes BI complex with I-Si and diffuses in the channel near S/D edges rapidly to happen TED. After annealing, B has pileup in the channel region at the edge of the S/D region. To control B TED, we need a new technique. (a) After As I/I (b) During annealing (c) After annealing WIMNACT WS 212, January 3, Titech 19

20 Co-implantation for diffusion control Co-I/I can suppress dopant diffusion and achieve shallower Xj. Better short channel effect and better device characteristics. F I/I for PFET: 5E14-2E15 Co-I/I for shallow N+ junction Fluorine co-i/i for shallow P+ junction WIMNACT WS 212, January 3, Titech 2

21 Carbon co-implantation for diffusion control Carbon co-i/i can control dopant diffusion for NFET. Better short channel effect and on-current by C co-i/i WIMNACT WS 212, January 3, Titech C.F. Tan et al., VLSI-TSA 28 21

22 σ V T [mv] Effect of co-i/i method There are several reports for diffusion control by using Nitrogen, Silicon, Fluorine, and Carbon. We have tried co-i/i method to mitigate Vth variation. However, co-i/i using Nitrogen, Silicon and Fluorine showed no effect to mitigate Vth variation. 15 N co-i/i Si co-i/i F co-i/i 1 Ref Tinv*(V T +V )/LW [nm.5 V.5 µm -1 ] WIMNACT WS 212, January 3, Titech 22

23 Carbon co-i/i for Variation mitigation V th [mv] C co-i/i has improved reverse short channel effect w/o performance degradation for NFET. Furthermore, C co-i/i has mitigated Vth variation of NFET. This is because Boron TED (Transient Enhanced Diffusion) in channel can be suppressed. 5 4 w/o C co-imp B VT = With C co-imp B VT = T INV (V th +V )/LW [nm.5 V.5 μ m -1 ] T.Tsunomura et al., VLSI Symp 29, p.11. WIMNACT WS 212, January 3, Titech 23

24 3D Atom Probe Analysis of Si-MOSFET 3D Atom probe method can analyze Si-MOSFET structure, including gate insulator. RDF in channel can be measured by 3D Atom Probe. Position-sensitive detector 位置敏感検出器 局所電極 Local electrode V extraction V total Z Y X Laser Beam 試料 ~1nm Specimen 3D Atom Probe System WIMNACT WS 212, January 3, Titech 24

25 Atom probe analysis of Boron diffusion Carbon co-i/i analysis revealed that Boron and carbon coclusters formed around the projection range of boron Boron TED was suppressed by those. Position-sensitive detector 位置敏感検出器 Local electrode 局所電極 V extraction V total Z Y X Laser Beam 試料 ~1nm Specimen 3D APT System Y. Shimizu et al., APL, 98, 23211, 211. WIMNACT WS 212, January 3, Titech 25

26 Summary Variation is the most important issue for the Advanced CMOS & LSI s. New variation evaluation method, Takeuchi plot, is very useful. Boron TED can be the origin of the larger Vth variation of NFET. To mitigate this variation of NFET, Carbon co-i/i technique is very useful. WIMNACT WS 212, January 3, Titech 26