FDSOI for Low Power System on Chip. M.HAOND STMicroelectronics, Crolles, France

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Bridget Short
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1 FDSOI for Low Power System on Chip M.HAOND STMicroelectronics, Crolles, France

2 OUTLINE Introduction : Motivations for FDSOI FDSOI Presentation & Short Channel control MOS VT Construction Performance Analysis 28FDSOI Silicon Results Scalability Summary

3 OUTLINE Introduction : Motivations for FDSOI FDSOI Presentation & Short Channel control MOS VT Construction Performance Analysis 28FDSOI Silicon Results Scalability Summary

4 4 Different Applications Different Needs SOC MULTI-FUNCTIONAL Mobile Internet Device High-Speed >2GHz Low Operation Vdd Low Stdby Leakage MPU MONO-FUNCTIONAL Computers, Servers High-Speed >>2GHz High Operation Vdd High Stdby Leakage Setup Box Video Computers, Servers Audio Photo Gaming, GPS different technologies needed

5 Speed, P dyn P stat, Switchoff SoC Elements High speed Logic Critical leakage edram envm SRAM Density, Process, compatibility Density, Speed, P stat Ft, Fmax, ESD High voltage Analog/ RF Ft, Fmax, gain

6 Computing Performance Trend Core 2 Quad 3.00 GHz + Core GHz + Tablets 2.5 GHz + Pentium 4 1 GHz MHz Basic phone 90 s Courtesy, P. Dautriche, ESSDERC 2011 inv. talk

7 OUTLINE Introduction : Motivations for FDSOI FDSOI Presentation & Short Channel control MOS VT Construction Performance Analysis 28FDSOI Silicon Results Scalability Summary

8 SmartCut Process for SOI (Courtesy SOITEC) 8

9 9 PDSOI vs FDSOI PDSOI FDSOI Thick Silicon film ~50-70nm and BOX ~150nm CMOS Scaling equals to Bulk Floating body effects Doped channel Ultra Thin Silicon film ~5-7nm Ultra Thin BOX (25nm) Scaling better than bulk No floating body (memory) effect Undoped channel (Analog, variability) Hybridation easy

V th UTBB/FDSOI Electrostatics (1) 0.4 0.3 DIBL V D = 0.

1 V D =V DD 0 10 Lnom 100 1000 L (nm) Bulk Thin Body SOI Bulk SOI DIBL DIBL = = 0.8 0.

10 V th UTBB/FDSOI Electrostatics (1) DIBL V D = 0.1V V th Xj T dep T Si T BOX th (V) V D =V DD 0 10 Lnom L (nm) Bulk Thin Body SOI Bulk SOI DIBL DIBL = = e Si e ox e Si e ox X 2 j L2 el T 2 Si L2 el Tox Lel Tox Lel Tdep Lel TSi Lel Vds Vds T. Skotnicki et al. IEEE EDL, March 88 & IEDM 1994 T si T dep,x j

11 UTBB/FDSOI Electrostatics (2) Excellent Electrostatic Control is obtained by optimizing Si (Body) Thickness vs MOS LGate V. Barral et al., IEDM 2007 (CEA-LETI/ST)

12 12 FDSOI : better Short Channel control ID Xj T dep T Si T BOX IL2 IL1 Bulk Thin Body SOI S2 S1 VT FDSOI : Short Channel effects controlled by the SOI film thickness Subthreshold slope lower for same Vt, leakage (Ioff) lower Static Power gain DIBL reduced for same Leakage : Vt lin lower VG Speed gain

13 OUTLINE Introduction : Motivations for FDSOI FDSOI Presentation & Short Channel control MOS VT Construction Performance Analysis 28FDSOI Silicon Results Scalability Summary

14 Multi-Vt with UTBB/FDSOI How to adjust V th in UTBB/FDSOI? Fm : Gate Metal Workfunction adjustment GP : set up an Equivalent Back-Gate Doping (D) or Counter Doping (CD) Back-Biasing (BB)

15 15 GP implant Use of Ground plane implants for Vt adjustments : Low to High NMOS G PMOS G N+ N+ P+ P+ Si - film BOX Si - film BOX N+ n/p - type n/p - type P+ n - type well p - type well Substrate P

16 FDSOI Devices Construction Well Tie Opening for FBB (new mask) S T I Si

17 FDSOI Devices FDSOI Devices Construction Well Definition Si pwell nwell

18 FDSOI Devices FDSOI Devices Construction GP LVT, RVT, HVT nhvt SRAM nrvt nlvt phvt SRAM prvt plvt Si pgp ngp ngp ngp pgp pgp GP pwell nwell

19 FDSOI Devices nhvt SRAM FDSOI Devices Construction High K Dielectric Deposition & Gates Definition : MetalN & MetalP (~1/4 Gap) nrvt nlvt phvt SRAM prvt plvt Si pgp ngp ngp ngp pgp pgp GP pwell nwell

20 FDSOI Devices FDSOI Devices Construction Source/Drain & Well Ties Implants & Anneal nhvt SRAM nrvt nlvt phvt SRAM prvt plvt Si P+ pgp ngp ngp ngp pgp pgp GP N+ pwell nwell

21 21 FDSOI/UTBB Structure UTBB-SOI : Ultra Thin Body (FD) and BOX SOI gate 3- Junctions 2-Gate Material 1- Film & Box 7- Isolation 6- Body Bias Thin Silicon film Thin Silicon Channel 4- Ground-Plane 5- Hybrid/Bulk Burried Si-substrate 25nm UTBOX device

22 Body (Back) Biasing V b =0 FBB RBB nmos Normal Speed + Pstat - pmos V b = V dd FBB RBB FBB Forward Body Bias RBB Reverse Body Bias As BOX GPN - As As As B BOX GPP - In B p n Vsub(p)=0 FBB RBB

23 OUTLINE Introduction : Motivations for FDSOI FDSOI Presentation & Short Channel control MOS VT Construction Performance Analysis 28FDSOI Silicon Results Scalability Summary

24 24 Technology Benchmark: 28nm FDSOI vs Bulk performances A9 critical TT process & 25C +40%

25 OUTLINE Introduction : Motivations for FDSOI FDSOI Presentation & Short Channel control MOS VT Construction Performance Analysis 28FDSOI Silicon Results Scalability Summary

26 28nm UTBB SOI Devices TEM

27 Iddq [na/stage] Tp (s) 28FDSOI vs 28LP Bulk : Silicon results 28FDSOI w/o BB 28LP 1.5E E E E E % w. BB -10% -30% Delay [ps/transition] 1E-11 9E-12 8E-12 RBB 0.5V RBB 0.3V No BB FBB 0.3V FBB 0.5V RO GO1 LVT (FO1, 1V Significant Tp reduction with FDSOI for a same leakage FBB helps improving RO delay by 10% 27

28 s(dvt) (V) 28FDSOI : Matching Factor 0.06 Pelgrom plot LP_LVT 28FDSOI /sqrt(WL) (1/µm) Avt is reduced by 40% in FDSOI Very useful for Vmin SRAM. Target : -100mV vs Bulk

29 OUTLINE Introduction : Motivations for FDSOI FDSOI Presentation & Short Channel control MOS VT Construction Performance Analysis 28FDSOI Silicon Results Scalability Summary

30 30 Future = Fully DepletedDevices FinFET and UTBB SOI look like one another : just a rotation. Ultimately they converge to the same structure when scaling BOX to TOX FinFET UTBB SOI

31 31 EXCELLENT SCALABILITY BOX scaling is an additional tool for FDSOI BOX scaling enables FDSOI scalability down to 8 nm with T Si not thinner than ~ 6nm NEW HK/MG Module IS STILL MANDATORY For SCALABILITY BOX=7.5nm Lg= 10nm BOX=10nm BOX=25nm O. Faynot et. al. FDSOI Workshop Oct. 15, 2009; Courtesy of CEA-LETI QUANTUM REALM

32 Body Factor (V/V) Estimated BOX Thickness 32 BOX Thickness Impact on Body Bactor 0,12 0,1 0,08 0,06 0,04 0,02 Tsi=5nm Tsi=6nm N Tsi=6nm Tinv=1.1nm N Tsi=5nm Tinv=1.1nm P Tsi=6nm Tinv=1.1nm P Tsi=5nm Tinv=1.1nm P Tsi=5nm Tinv=1.3nm BF(Tsi=6nm)>BF(Tsi=5nm) : Back channel conduction signature 0 0 0,05 0,1 0,15 TBox (um) Data : M.A. Jaud (Green=TBOX for 100mV/V) 28nm 20nm 14nm 10nm Technological Node (nm) BF increases for smaller TBOX In order to keep a constant 100mV/V BF, BOX thickness target is : 28nm node : 20-25nm 20nm node : 15-20nm 14nm node : 10-15nm 10nm node : <10nm

33 33 Transistor Architecture R&D Trends 16nm/14nm 11nm/10nm Record Performance Nanodot FET (ST VLSI 2009) 8nm/7nm HQS GAA Devices (ST IEDM 2010) 22/20nm 25nm FDSOI ( ST/IBM VLSI 2010) 15nm FDSOI ( ST/LETI VLSI 2010) FinFET ( ST/IMEC VLSI 2006) 32/28nm 28nm Low Power (ST/IBM IEDM 2009) Hybrid UTB² /Bulk (ST/LETI IEDM 2009) Fully Depleted SOI with Hybrid Bulk Bulk w/ enhanced stressors 2 nd Generation MGHK (Gate Last) Improved junctions Fully Depleted SOI with Hybrid Bulk Fully Depleted SOI with Ultra Thin BOX and Stressors FinFETs Self Aligned Planar Double Gates structures Gate First Metal Gate High-K

34 OUTLINE Introduction : Motivations for FDSOI FDSOI Presentation & Short Channel control MOS VT Construction Performance Analysis 28FDSOI Silicon Results Scalability Summary

35 Summary Performance needs are increased together with Power consumption control UTBB / FDSOI is a key technology for adressing High speed and leakage control Fully depleted Devices are key for coming technology nodes and UTBB/FDSOI is clearly an answer to the needs

36 Thank You! 36

Lecture 8. Thin-Body MOSFET s Process II. Source/Drain Technologies Threshold Voltage Engineering

Lecture 8. Thin-Body MOSFET s Process II. Source/Drain Technologies Threshold Voltage Engineering Atom Probe Tomography for Dopants in FinFETs Lecture 8 A.K. Kambham (imec), VLSI-T 2012 Thin-Body MOSFET s Process II Source/Drain Technologies Threshold Voltage Engineering Reading: multiple research