IOLTS th IEEE International On-Line Testing Symposium

Size: px
Start display at page:

Download "IOLTS th IEEE International On-Line Testing Symposium"

Transcription

1 IOLTS th IEEE International On-Line Testing Symposium Exp. comparison and analysis of the sensitivity to laser fault injection of CMOS FD-SOI and CMOS bulk technologies J.M. Dutertre 1, V. Beroulle 2, P. Candelier 3, L.B. Faber 3, M.L. Flottes 4, P. Gendrier 3, D. Hély 2, R. Leveugle 5, P. Maistri 5, G. Di Natale 4, A. Papadimitriou 2, B. Rouzeyre 4 Wednesday, July 4 th 2018 Platja D Aro, Costa Brava, Spain (1) (2) (3) (4) (5)

2 Laser Fault Injection CMOS bulk vs FD-SOI! Who s interested in laser fault injection? " Radiation effects community since 1967! ICs for spatial & aircraft applications! Single Event Effects (SEEs) induced by ionizing particles! Pulsed laser (ps range) used for SEE emulation! Various countermeasures: techno. & process? (small market) CMOS Silicon On Insulator (SOI) less sensitive to SEEs The Use of Lasers to Simulate Radiation-Induced Transients in Semiconductor Devices and Circuits, D. Habing,

3 Laser Fault Injection CMOS bulk vs FD-SOI! Who s interested in laser fault injection? " Hardware Security community! Concept of fault injection: 1997 D. Boneh et al.! Laser fault injection: 2002 S. Skorobogatov et al.! Technological countermeasure?! SOI to mitigate laser fault injection! Dev. of a dedicated process is expensive On the Importance of Checking Cryptographic Protocols for Faults, Dan Boneh et al, 1997 Optical Fault Induction Attacks, S. Skorobogatov et al,

4 Laser Fault Injection CMOS bulk vs FD-SOI " UTBB FD-SOI (Ultra-Thin Body and Box Fully-Depleted SOI)! is now a mature technology (ST Micro, Samsung, GlobalFoundries)! Ultra Low Power application (low static leakage, body biasing)! Laser-induced faults/sees mitigation properties? Topic of this talk: FD-SOI laser fault injection mitigation properties, and comparison with CMOS bulk, on experimental basis at the 28 nm tech. node 4

5 Outline I. Introduction II. Theory of laser fault injection III. State of the art IV. Laser sensitivity assessment of FD-SOI and CMOS bulk V. Conclusion 5

6 Outline I. Introduction II. Theory of laser fault injection! Mechanism, photoelectric effect! LFI sensitivity of CMOS bulk! LFI sensitivity of CMOS FD-SOI III. State of the art IV. Laser sensitivity assessment of FD-SOI and CMOS bulk V. Conclusion 6

7 ! Photoelectric effect: transient current generation Theory of laser fault injection Laser Drain ( Gnd V DD ) I max Transient current Current (ma) E N + diffusion Depletion region P substrate (Gnd) Current peak Drift current Time (ns) Laser sensitive areas: reverse biased PN junctions 7

8 Theory of laser fault injection! Fault injection mechanism: CMOS bulk inverter transient current # voltage transient (SET, single event transient) in 0 Metal 1 MOS gate out 1 => 0 C to Gnd to Vdd P+ N+ N+ P+ P+ N+ P substrate NMOS OFF PMOS ON N well laser beam Voltage transient # fault (prop. into DFF, or memory flip) 8

9 Theory of laser fault injection! LFI sensitivity of CMOS bulk nmos pmos B (gnd) S G D D G S B (Vdd) P+ P substrate N+ (a) N+ (1) P+ P+ N+ (2) (b) Nwell (c) (3) PN junctions = laser sensitive ares of CMOS devices: 3 types Parasitic bipolar transistors: 3 types (a), (b), (c) (1), (2), (3) 9

10 Theory of laser fault injection! CMOS FD-SOI structure Regular Vt transistors G NMOS G gnd B (gnd) S D D S B (Vdd) P+ STI P+ N+ N+ P+ P+ box box STI STI STI STI N+ Pwell Nwell P substrate P+ type Si P type Si P substrate gate N+ type Si N type Si Insulator (STI or box or gate oxide) 10

11 Theory of laser fault injection! CMOS FD-SOI structure Regular Vt transistors gnd P+ STI B (gnd) P+ G S D D Channel: Sintrinsic B (Vdd) Si N+ N+ P+ P+ box box STI STI STI STI N+ Pwell NMOS G (thickness < 10 nm) Nwell Reduced charge collection volume Reduced laser sensitivity? P substrate Isolation box (thickness < 30nm) P+ type Si P type Si P substrate gate N+ type Si N type Si Insulator (STI or box or gate oxide) 11

12 Theory of laser fault injection! CMOS FD-SOI structure Regular Vt transistors Laser sensitive PN junctions: 1 type (1) G G gnd B (gnd) S D D S B (Vdd) P+ STI P+ N+ N+ P+ P+ box box STI STI STI STI N+ Pwell Nwell (1) P substrate 12

13 Theory of laser fault injection! Laser sensitivity of FD-SOI V S = 0 Source N+ emitter e Channel Gate oxide V FG = 0 base h + collector e V D> 0 Drain N+ BOX Pwell V BG = 0 Parasitic bipolar NPN transistor Laser induced charge carriers + holes: (h h + ) electrons: (e e) - 13

14 Theory of laser fault injection! Laser sensitivity of FD-SOI V S = 0 Source N+ emitter e Channel Gate oxide V FG = 0 base h + collector e V D> 0 Drain N+ BOX Pwell V BG = 0 Parasitic bipolar NPN transistor amplification effect on the laser-induced current 14

15 Theory of laser fault injection! Laser sensitivity of FD-SOI vs CMOS bulk Advantages of FD-SOI (rule of thumbs): isolation box under transistors x10 (factor in lower sensitivity) smaller sensitive area x2 (factor in lower sensitivity) # less charge sharing between transistors. Parasitic bipolar amplification effect on the laser-induced current: # there are still faults # x10 and x2 may not be fullfilled Radiation hardness of FDSOI and FinFET technologies, M.L. Alles et al,

16 Outline I. Introduction II. Theory of laser fault injection III. State of the art! Radiation focused State-of-the-art! Security focused State-of-the-art IV. Laser sensitivity assessment of FD-SOI and CMOS bulk V. Conclusion 16

17 State-of-the-art " Radiation focused state-of-the-art! Neutrons, heavy ions, laser! Laser for SEE emulation: 1 µm diameter, ps range! SOI or FD-SOI, 0.2 µm to 28 nm! Mainly on elementary test patterns 1-2 orders of magnitude in favor of SOI/FD-SOI 17

18 State-of-the-art " Security focused state-of-the-art! CMOS bulk vs CMOS FD-SOI at 28 nm! Elementary test patterns: wells or transistors! Laser settings: 1,064 nm, 1-5 µm diameter, ns & µs ranges 1 order of magnitude in terms of peak current FD-SOI: smaller extension of sensitive areas 18

19 Outline I. Introduction II. Theory of laser fault injection III. State of the art IV. Laser sensitivity assessment of FD-SOI and CMOS bulk! Experimental setup! Radiation-centric experimental results! Attack-centric experimental results V. Conclusion 19

20 " Experimental setup Laser sensitivity of FD-SOI vs CMOS bulk 20

21 Laser sensitivity of FD-SOI vs CMOS bulk " Experimental setup Backside injection Pulse width: 30 ps up to 100 nj Wavelength: 1,030 nm Pulse width: ns 5-50 ns, max. power 1 W 50 ns 1 s, max. power 3 W Wavelength: 1,064 nm Spot size: 1µm or 5 µm 21

22 " Test chips CMOS 28 nm! Target: AES implementation (with parity-based CM) Vdd = 1.2 V IR microphotography (rear side), obj. x20 Laser sensitivity of FD-SOI vs CMOS bulk CMOS bulk Thickness ~ 100 µm CMOS FD-SOI Thickness ~ 100 µm 22

23 " Experiments description Laser sensitivity of FD-SOI vs CMOS bulk Laser head y x Laser fault injection threshold + 2,000 injections attempts per test Full functional IP running at 100 MHz 23

24 Laser sensitivity of FD-SOI vs CMOS bulk " Radiation-centric experimental results! Laser parameters: 30 ps, 1 µm laser spot diameter Laser fault injection threshold CMOS bulk CMOS FD-SOI [W] [mw/µm 2 ] [W] [mw/µm 2 ] Laser: 30 ps / 1 µm 0.2 nj 16.9 pj/µm nj 50.6 pj/µm 2 x3 24

25 Laser sensitivity of FD-SOI vs CMOS bulk " Radiation-centric experimental results! Laser parameters: 30 ps, 1 µm laser spot diameter 30 ps, 5 µm laser spot diameter Laser fault injection threshold CMOS bulk CMOS FD-SOI [W] [mw/µm 2 ] [W] [mw/µm 2 ] Laser: 30 ps / 1 µm 0.2 nj 16.9 pj/µm nj 50.6 pj/µm 2 Laser: 30 ps / 5 µm 0.3 nj 2.2 pj/µm nj 15.4 pj/µm 2 FD-SOI vs bulk: x3 factor sensitivity decrease disappointing at 1 µm, FD-SOI vs bulk: x7 factor at 5 µm close to state-of-the-art. x7 25

26 Laser sensitivity of FD-SOI vs CMOS bulk " Attack-centric experimental results! Laser parameters: 10 ns, 1 µm laser spot diameter Laser fault injection threshold CMOS bulk CMOS FD-SOI [W] [mw/µm 2 ] [W] [mw/µm 2 ] Laser: 10 ns / 1 µm

27 Laser sensitivity of FD-SOI vs CMOS bulk " Attack-centric experimental results! Laser parameters: 10 ns, 1 µm laser spot diameter 10 ns, 5 µm laser spot diameter Laser fault injection threshold CMOS bulk CMOS FD-SOI [W] [mw/µm 2 ] [W] [mw/µm 2 ] Laser: 10 ns / 1 µm Laser: 10 ns / 5 µm No fault (1W limit) 27

28 Laser sensitivity of FD-SOI vs CMOS bulk " Attack-centric experimental results! Laser parameters: 10 ns, 1 µm -10 ns, 5 µm 50 ns, 5 µm laser spot diameter Laser fault injection threshold CMOS bulk CMOS FD-SOI [W] [mw/µm 2 ] [W] [mw/µm 2 ] Laser: 10 ns / 1 µm Laser: 10 ns / 5 µm Laser: 50 ns / 5 µm x7 28

29 Outline I. Introduction II. Theory of laser fault injection III. State of the art IV. Laser sensitivity assessment of FD-SOI and CMOS bulk V. Conclusion 29

30 Conclusion " Analysis Laser fault injection threshold CMOS bulk CMOS FD-SOI [W] [mw/µm 2 ] [W] [mw/µm 2 ] Laser: 30 ps / 1 µm 0.2 nj 16.9 pj/µm nj 50.6 pj/µm 2 Laser: 30 ps / 5 µm 0.3 nj 2.2 pj/µm nj 15.4 pj/µm 2 Laser: 10 ns / 1 µm Laser: 10 ns / 5 µm Laser: 50 ns / 5 µm Advantage of CMOS FD-SOI over CMOS bulk: 1-2 order of magnitude of the SotA not fulfilled, At 1 µm spot diameter: a factor 2-3 At 5 µm spot diameter: a factor 7 30

31 Conclusion " Analysis! FD-SOI vulnerability? G G gnd B (gnd) S D D S B (Vdd) P+ STI P+ N+ N+ P+ P+ box box STI STI STI STI N+ P substrate Pwell Nwell (1) Laser sensitive PN junctions: (1) Laser-induced Vdd drop? 31

32 " Analysis! Interest of a 2-3 lower laser sensitivity? Conclusion Intrinsic to FD-SOI, Equivalent to a similar increase in laser sensors efficiency, eg BBICS: 32

33 Thank you for your attention Work funded by the ANR: LIESSE project J.M. Dutertre 1, V. Beroulle 2, P. Candelier 3, L.B. Faber 3, M.L. Flottes 4, P. Gendrier 3, D. Hély 2, R. Leveugle 5, P. Maistri 5, G. Di Natale 4, A. Papadimitriou 2, B. Rouzeyre 4 (1) (2) (3) (4) (5)

Laser attacks on integrated circuits: from CMOS to FD-SOI

Laser attacks on integrated circuits: from CMOS to FD-SOI DTIS 2014 9 th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Laser attacks on integrated circuits: from CMOS to FD-SOI J.-M. Dutertre 1, S. De Castro 1, A. Sarafianos

More information

Improving the ability of bulk built-in current sensors to detect Single Event Effects by using triple-well CMOS

Improving the ability of bulk built-in current sensors to detect Single Event Effects by using triple-well CMOS ESREF 2014 25th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis Improving the ability of bulk built-in current sensors to detect Single Event Effects by using triple-well

More information

Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated. circuits

Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated. circuits Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuits Stephan De Castro, Jean-Max Dutertre, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre

More information

Simulation of High Resistivity (CMOS) Pixels

Simulation of High Resistivity (CMOS) Pixels Simulation of High Resistivity (CMOS) Pixels Stefan Lauxtermann, Kadri Vural Sensor Creations Inc. AIDA-2020 CMOS Simulation Workshop May 13 th 2016 OUTLINE 1. Definition of High Resistivity Pixel Also

More information

INTRODUCTION TO MOS TECHNOLOGY

INTRODUCTION TO MOS TECHNOLOGY INTRODUCTION TO MOS TECHNOLOGY 1. The MOS transistor The most basic element in the design of a large scale integrated circuit is the transistor. For the processes we will discuss, the type of transistor

More information

Session 3: Solid State Devices. Silicon on Insulator

Session 3: Solid State Devices. Silicon on Insulator Session 3: Solid State Devices Silicon on Insulator 1 Outline A B C D E F G H I J 2 Outline Ref: Taurand Ning 3 SOI Technology SOl materials: SIMOX, BESOl, and Smart Cut SIMOX : Synthesis by IMplanted

More information

Design cycle for MEMS

Design cycle for MEMS Design cycle for MEMS Design cycle for ICs IC Process Selection nmos CMOS BiCMOS ECL for logic for I/O and driver circuit for critical high speed parts of the system The Real Estate of a Wafer MOS Transistor

More information

DesignofaRad-HardLibraryof DigitalCellsforSpaceApplications

DesignofaRad-HardLibraryof DigitalCellsforSpaceApplications DesignofaRad-HardLibraryof DigitalCellsforSpaceApplications Alberto Stabile, Valentino Liberali and Cristiano Calligaro stabile@dti.unimi.it, liberali@dti.unimi.it, c.calligaro@redcatdevices.it Department

More information

Electrostatic Discharge and Latch-Up

Electrostatic Discharge and Latch-Up Connexions module: m1031 1 Electrostatic Discharge and Latch-Up Version 2.10: Jul 3, 2003 12:00 am GMT-5 Bill Wilson This work is produced by The Connexions Project and licensed under the Creative Commons

More information

Lecture #29. Moore s Law

Lecture #29. Moore s Law Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday

More information

Electrical model of an NMOS body biased structure in triple-well technology under photoelectric laser stimulation

Electrical model of an NMOS body biased structure in triple-well technology under photoelectric laser stimulation Electrical model of an NMOS body biased structure in triple-well technology under photoelectric laser stimulation N Borrel, C Champeix, M Lisart, A Sarafianos, E Kussener, W Rahajandraibe, Jean-Max Dutertre

More information

Session 10: Solid State Physics MOSFET

Session 10: Solid State Physics MOSFET Session 10: Solid State Physics MOSFET 1 Outline A B C D E F G H I J 2 MOSCap MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor: Al (metal) SiO2 (oxide) High k ~0.1 ~5 A SiO2 A n+ n+ p-type Si (bulk)

More information

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI 1 Integrated diodes pn junctions of transistor structures can be used as integrated diodes. The choice of the junction is limited by the considerations of switching speed and breakdown voltage. The forward

More information

Device design methodology to optimize low-frequency Noise in advanced SOI CMOS technology

Device design methodology to optimize low-frequency Noise in advanced SOI CMOS technology Device design methodology to optimize low-frequency Noise in advanced SOI CMOS technology Prem Prakash Satpathy*, Dr. VijayNath**, Abhinandan Jain*** *Lecturer, Dept. of ECE, Cambridge Institute of Technology,

More information

Department of Electrical Engineering IIT Madras

Department of Electrical Engineering IIT Madras Department of Electrical Engineering IIT Madras Sample Questions on Semiconductor Devices EE3 applicants who are interested to pursue their research in microelectronics devices area (fabrication and/or

More information

Basic Fabrication Steps

Basic Fabrication Steps Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor

More information

Electrical Characterization of a Second-gate in a Silicon-on-Insulator Transistor

Electrical Characterization of a Second-gate in a Silicon-on-Insulator Transistor Electrical Characterization of a Second-gate in a Silicon-on-Insulator Transistor Antonio Oblea: McNair Scholar Dr. Stephen Parke: Faculty Mentor Electrical Engineering As an independent double-gate, silicon-on-insulator

More information

CHAPTER 7 A BICS DESIGN TO DETECT SOFT ERROR IN CMOS SRAM

CHAPTER 7 A BICS DESIGN TO DETECT SOFT ERROR IN CMOS SRAM 131 CHAPTER 7 A BICS DESIGN TO DETECT SOFT ERROR IN CMOS SRAM 7.1 INTRODUCTION Semiconductor memories are moving towards higher levels of integration. This increase in integration is achieved through reduction

More information

UNIT 3: FIELD EFFECT TRANSISTORS

UNIT 3: FIELD EFFECT TRANSISTORS FIELD EFFECT TRANSISTOR: UNIT 3: FIELD EFFECT TRANSISTORS The field effect transistor is a semiconductor device, which depends for its operation on the control of current by an electric field. There are

More information

MEASUREMENT AND INSTRUMENTATION STUDY NOTES UNIT-I

MEASUREMENT AND INSTRUMENTATION STUDY NOTES UNIT-I MEASUREMENT AND INSTRUMENTATION STUDY NOTES The MOSFET The MOSFET Metal Oxide FET UNIT-I As well as the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor available

More information

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-

More information

420 Intro to VLSI Design

420 Intro to VLSI Design Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem

More information

Silicon on Insulator (SOI) Spring 2018 EE 532 Tao Chen

Silicon on Insulator (SOI) Spring 2018 EE 532 Tao Chen Silicon on Insulator (SOI) Spring 2018 EE 532 Tao Chen What is Silicon on Insulator (SOI)? SOI silicon on insulator, refers to placing a thin layer of silicon on top of an insulator such as SiO2. The devices

More information

UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press

UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press UNIT-1 Bipolar Junction Transistors Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press Figure 6.1 A simplified structure of the npn transistor. Microelectronic Circuits, Sixth

More information

Reliability of deep submicron MOSFETs

Reliability of deep submicron MOSFETs Invited paper Reliability of deep submicron MOSFETs Francis Balestra Abstract In this work, a review of the reliability of n- and p-channel Si and SOI MOSFETs as a function of gate length and temperature

More information

I E I C since I B is very small

I E I C since I B is very small Figure 2: Symbols and nomenclature of a (a) npn and (b) pnp transistor. The BJT consists of three regions, emitter, base, and collector. The emitter and collector are usually of one type of doping, while

More information

Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism;

Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism; Chapter 3 Field-Effect Transistors (FETs) 3.1 Introduction Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism; The concept has been known

More information

Monolithic Pixel Sensors in SOI technology R&D activities at LBNL

Monolithic Pixel Sensors in SOI technology R&D activities at LBNL Monolithic Pixel Sensors in SOI technology R&D activities at LBNL Lawrence Berkeley National Laboratory M. Battaglia, L. Glesener (UC Berkeley & LBNL), D. Bisello, P. Giubilato (LBNL & INFN Padova), P.

More information

Device Technologies. Yau - 1

Device Technologies. Yau - 1 Device Technologies Yau - 1 Objectives After studying the material in this chapter, you will be able to: 1. Identify differences between analog and digital devices and passive and active components. Explain

More information

6.012 Microelectronic Devices and Circuits

6.012 Microelectronic Devices and Circuits Page 1 of 13 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Microelectronic Devices and Circuits Final Eam Closed Book: Formula sheet provided;

More information

Topic 3. CMOS Fabrication Process

Topic 3. CMOS Fabrication Process Topic 3 CMOS Fabrication Process Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Lecture 3-1 Layout of a Inverter

More information

COLLECTOR DRAIN BASE GATE EMITTER. Applying a voltage to the Gate connection allows current to flow between the Drain and Source connections.

COLLECTOR DRAIN BASE GATE EMITTER. Applying a voltage to the Gate connection allows current to flow between the Drain and Source connections. MOSFETS Although the base current in a transistor is usually small (< 0.1 ma), some input devices (e.g. a crystal microphone) may be limited in their output. In order to overcome this, a Field Effect Transistor

More information

NAME: Last First Signature

NAME: Last First Signature UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 130: IC Devices Spring 2003 FINAL EXAMINATION NAME: Last First Signature STUDENT

More information

Southern Methodist University Dallas, TX, Southern Methodist University Dallas, TX, 75275

Southern Methodist University Dallas, TX, Southern Methodist University Dallas, TX, 75275 Single Event Effects in a 0.25 µm Silicon-On-Sapphire CMOS Technology Wickham Chen 1, Tiankuan Liu 2, Ping Gui 1, Annie C. Xiang 2, Cheng-AnYang 2, Junheng Zhang 1, Peiqing Zhu 1, Jingbo Ye 2, and Ryszard

More information

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

INTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH, DINDIGUL Volume 1, No 3, 2010

INTERNATIONAL JOURNAL OF APPLIED ENGINEERING RESEARCH, DINDIGUL Volume 1, No 3, 2010 Low Power CMOS Inverter design at different Technologies Vijay Kumar Sharma 1, Surender Soni 2 1 Department of Electronics & Communication, College of Engineering, Teerthanker Mahaveer University, Moradabad

More information

Solid State Devices- Part- II. Module- IV

Solid State Devices- Part- II. Module- IV Solid State Devices- Part- II Module- IV MOS Capacitor Two terminal MOS device MOS = Metal- Oxide- Semiconductor MOS capacitor - the heart of the MOSFET The MOS capacitor is used to induce charge at the

More information

Power Semiconductor Devices

Power Semiconductor Devices TRADEMARK OF INNOVATION Power Semiconductor Devices Introduction This technical article is dedicated to the review of the following power electronics devices which act as solid-state switches in the circuits.

More information

Fundamentals of Power Semiconductor Devices

Fundamentals of Power Semiconductor Devices В. Jayant Baliga Fundamentals of Power Semiconductor Devices 4y Spri ringer Contents Preface vii Chapter 1 Introduction 1 1.1 Ideal and Typical Power Switching Waveforms 3 1.2 Ideal and Typical Power Device

More information

BJT Amplifier. Superposition principle (linear amplifier)

BJT Amplifier. Superposition principle (linear amplifier) BJT Amplifier Two types analysis DC analysis Applied DC voltage source AC analysis Time varying signal source Superposition principle (linear amplifier) The response of a linear amplifier circuit excited

More information

Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018

Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 ECE 658 Sp 2018 Semiconductor Materials and Device Characterizations OUTLINE Background FinFET Future Roadmap Keeping up w/ Moore s Law

More information

UNIT-1 Fundamentals of Low Power VLSI Design

UNIT-1 Fundamentals of Low Power VLSI Design UNIT-1 Fundamentals of Low Power VLSI Design Need for Low Power Circuit Design: The increasing prominence of portable systems and the need to limit power consumption (and hence, heat dissipation) in very-high

More information

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o.

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o. Layout of a Inverter Topic 3 CMOS Fabrication Process V DD Q p Peter Cheung Department of Electrical & Electronic Engineering Imperial College London v i v o Q n URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk

More information

VLSI Design. Introduction

VLSI Design. Introduction VLSI Design Introduction Outline Introduction Silicon, pn-junctions and transistors A Brief History Operation of MOS Transistors CMOS circuits Fabrication steps for CMOS circuits Introduction Integrated

More information

Monolithic Pixel Detector in a 0.15µm SOI Technology

Monolithic Pixel Detector in a 0.15µm SOI Technology Monolithic Pixel Detector in a 0.15µm SOI Technology 2006 IEEE Nuclear Science Symposium, San Diego, California, Nov. 1, 2006 Yasuo Arai (KEK) KEK Detector Technology Project : [SOIPIX Group] Y. Arai Y.

More information

Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor

Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris,

More information

Topic 2. Basic MOS theory & SPICE simulation

Topic 2. Basic MOS theory & SPICE simulation Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris, Ch 2 & 5.1-5.3 Rabaey, Ch 3) URL: www.ee.ic.ac.uk/pcheung/

More information

Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor

Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris,

More information

Lecture Integrated circuits era

Lecture Integrated circuits era Lecture 1 1.1 Integrated circuits era Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell laboratories. In 1961, first IC was introduced. Levels of Integration:-

More information

Analog and Telecommunication Electronics

Analog and Telecommunication Electronics Politecnico di Torino - ICT School Analog and Telecommunication Electronics F2 Active power devices»mos»bjt» IGBT, TRIAC» Safe Operating Area» Thermal analysis 30/05/2012-1 ATLCE - F2-2011 DDC Lesson F2:

More information

MOS TRANSISTOR THEORY

MOS TRANSISTOR THEORY MOS TRANSISTOR THEORY Introduction A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain is modulated by a voltage applied to the

More information

FinFET vs. FD-SOI Key Advantages & Disadvantages

FinFET vs. FD-SOI Key Advantages & Disadvantages FinFET vs. FD-SOI Key Advantages & Disadvantages Amiad Conley Technical Marketing Manager Process Diagnostics & Control, Applied Materials ChipEx-2014, Apr 2014 1 Moore s Law The number of transistors

More information

Learning Outcomes. Spiral 2-6. Current, Voltage, & Resistors DIODES

Learning Outcomes. Spiral 2-6. Current, Voltage, & Resistors DIODES 26.1 26.2 Learning Outcomes Spiral 26 Semiconductor Material MOS Theory I underst why a diode conducts current under forward bias but does not under reverse bias I underst the three modes of operation

More information

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor

More information

SRM INSTITUTE OF SCIENCE AND TECHNOLOGY (DEEMED UNIVERSITY)

SRM INSTITUTE OF SCIENCE AND TECHNOLOGY (DEEMED UNIVERSITY) SRM INSTITUTE OF SCIENCE AND TECHNOLOGY (DEEMED UNIVERSITY) QUESTION BANK I YEAR B.Tech (II Semester) ELECTRONIC DEVICES (COMMON FOR EC102, EE104, IC108, BM106) UNIT-I PART-A 1. What are intrinsic and

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 MOS Transistor Theory Study conducting channel between

More information

Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore

Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore Semiconductor Memory: DRAM and SRAM Outline Introduction Random Access Memory (RAM) DRAM SRAM Non-volatile memory UV EPROM EEPROM Flash memory SONOS memory QD memory Introduction Slow memories Magnetic

More information

CONTENTS. 2.2 Schrodinger's Wave Equation 31. PART I Semiconductor Material Properties. 2.3 Applications of Schrodinger's Wave Equation 34

CONTENTS. 2.2 Schrodinger's Wave Equation 31. PART I Semiconductor Material Properties. 2.3 Applications of Schrodinger's Wave Equation 34 CONTENTS Preface x Prologue Semiconductors and the Integrated Circuit xvii PART I Semiconductor Material Properties CHAPTER 1 The Crystal Structure of Solids 1 1.0 Preview 1 1.1 Semiconductor Materials

More information

ITT Technical Institute. ET215 Devices 1. Unit 8 Chapter 4, Sections

ITT Technical Institute. ET215 Devices 1. Unit 8 Chapter 4, Sections ITT Technical Institute ET215 Devices 1 Unit 8 Chapter 4, Sections 4.4 4.5 Chapter 4 Section 4.4 MOSFET Characteristics A Metal-Oxide semiconductor field-effect transistor is the other major category of

More information

Mechanis m Faliures. Group Leader Jepsy 1)Substrate Biasing 2) Minority Injection. Bob 1)Minority-Carrier Guard Rings

Mechanis m Faliures. Group Leader Jepsy 1)Substrate Biasing 2) Minority Injection. Bob 1)Minority-Carrier Guard Rings Mechanis m Faliures Group Leader Jepsy 1)Substrate Biasing 2) Minority Injection As im 1)Types Of Guard Rings Sandra 1)Parasitics 2)Field Plating Bob 1)Minority-Carrier Guard Rings Shawn 1)Parasitic Channel

More information

THE METAL-SEMICONDUCTOR CONTACT

THE METAL-SEMICONDUCTOR CONTACT THE METAL-SEMICONDUCTOR CONTACT PROBLEM 1 To calculate the theoretical barrier height, built-in potential barrier, and maximum electric field in a metal-semiconductor diode for zero applied bias. Consider

More information

Structure Optimization of ESD Diodes for Input Protection of CMOS RF ICs

Structure Optimization of ESD Diodes for Input Protection of CMOS RF ICs JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.3, JUNE, 2017 ISSN(Print) 1598-1657 https://doi.org/10.5573/jsts.2017.17.3.401 ISSN(Online) 2233-4866 Structure Optimization of ESD Diodes for

More information

INTRODUCTION: Basic operating principle of a MOSFET:

INTRODUCTION: Basic operating principle of a MOSFET: INTRODUCTION: Along with the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor available whose Gate input is electrically insulated from the main current carrying

More information

Christian Boit TUB Berlin University of Technology Sect. Semiconductor Devices. 1

Christian Boit TUB Berlin University of Technology Sect. Semiconductor Devices. 1 Semiconductor Device & Analysis Center Berlin University of Technology Christian Boit TUB Berlin University of Technology Sect. Semiconductor Devices Christian.Boit@TU-Berlin.DE 1 Semiconductor Device

More information

VLSI Design. Introduction

VLSI Design. Introduction Tassadaq Hussain VLSI Design Introduction Outcome of this course Problem Aims Objectives Outcomes Data Collection Theoretical Model Mathematical Model Validate Development Analysis and Observation Pseudo

More information

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02 EE 5611 Introduction to Microelectronic Technologies Fall 2014 Thursday, September 04, 2014 Lecture 02 1 Lecture Outline Review on semiconductor materials Review on microelectronic devices Example of microelectronic

More information

MOSFET & IC Basics - GATE Problems (Part - I)

MOSFET & IC Basics - GATE Problems (Part - I) MOSFET & IC Basics - GATE Problems (Part - I) 1. Channel current is reduced on application of a more positive voltage to the GATE of the depletion mode n channel MOSFET. (True/False) [GATE 1994: 1 Mark]

More information

EE301 Electronics I , Fall

EE301 Electronics I , Fall EE301 Electronics I 2018-2019, Fall 1. Introduction to Microelectronics (1 Week/3 Hrs.) Introduction, Historical Background, Basic Consepts 2. Rewiev of Semiconductors (1 Week/3 Hrs.) Semiconductor materials

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

The Effect of Threshold Voltages on the Soft Error Rate. - V Degalahal, N Rajaram, N Vijaykrishnan, Y Xie, MJ Irwin

The Effect of Threshold Voltages on the Soft Error Rate. - V Degalahal, N Rajaram, N Vijaykrishnan, Y Xie, MJ Irwin The Effect of Threshold Voltages on the Soft Error Rate - V Degalahal, N Rajaram, N Vijaykrishnan, Y Xie, MJ Irwin Outline Introduction Soft Errors High Threshold ( V t ) Charge Creation Logic Attenuation

More information

Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer

Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer Mr. Y.Satish Kumar M.tech Student, Siddhartha Institute of Technology & Sciences. Mr. G.Srinivas, M.Tech Associate

More information

Cosmic Rays induced Single Event Effects in Power Semiconductor Devices

Cosmic Rays induced Single Event Effects in Power Semiconductor Devices Cosmic Rays induced Single Event Effects in Power Semiconductor Devices Giovanni Busatto University of Cassino ITALY Outline Introduction Cosmic rays in Space Cosmic rays at Sea Level Radiation Effects

More information

Active Pixel Sensors Fabricated in a Standard 0.18 um CMOS Technology

Active Pixel Sensors Fabricated in a Standard 0.18 um CMOS Technology Active Pixel Sensors Fabricated in a Standard.18 um CMOS Technology Hui Tian, Xinqiao Liu, SukHwan Lim, Stuart Kleinfelder, and Abbas El Gamal Information Systems Laboratory, Stanford University Stanford,

More information

1 FUNDAMENTAL CONCEPTS What is Noise Coupling 1

1 FUNDAMENTAL CONCEPTS What is Noise Coupling 1 Contents 1 FUNDAMENTAL CONCEPTS 1 1.1 What is Noise Coupling 1 1.2 Resistance 3 1.2.1 Resistivity and Resistance 3 1.2.2 Wire Resistance 4 1.2.3 Sheet Resistance 5 1.2.4 Skin Effect 6 1.2.5 Resistance

More information

Measurement results of DIPIX pixel sensor developed in SOI technology

Measurement results of DIPIX pixel sensor developed in SOI technology Measurement results of DIPIX pixel sensor developed in SOI technology Mohammed Imran Ahmed a,b, Yasuo Arai c, Marek Idzik a, Piotr Kapusta b, Toshinobu Miyoshi c, Micha l Turala b a AGH University of Science

More information

Objective Type Questions 1. Why pure semiconductors are insulators at 0 o K? 2. What is effect of temperature on barrier voltage? 3.

Objective Type Questions 1. Why pure semiconductors are insulators at 0 o K? 2. What is effect of temperature on barrier voltage? 3. Objective Type Questions 1. Why pure semiconductors are insulators at 0 o K? 2. What is effect of temperature on barrier voltage? 3. What is difference between electron and hole? 4. Why electrons have

More information

NEW INSIGHTS INTO THE TOTAL DOSE RESPONSE OF FULLY- DEPLETED PLANAR AND FINFET SOI TRANSISTORS

NEW INSIGHTS INTO THE TOTAL DOSE RESPONSE OF FULLY- DEPLETED PLANAR AND FINFET SOI TRANSISTORS NEW INSIGHTS INTO THE TOTAL DOSE RESPONSE OF FULLY- DEPLETED PLANAR AND FINFET SOI TRANSISTORS By Farah El Mamouni Thesis Submitted to the Faculty of the Graduate school of Vanderbilt University in partial

More information

Semiconductor Physics and Devices

Semiconductor Physics and Devices Metal-Semiconductor and Semiconductor Heterojunctions The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of two major types of transistors. The MOSFET is used in digital circuit, because

More information

LSI ON GLASS SUBSTRATES

LSI ON GLASS SUBSTRATES LSI ON GLASS SUBSTRATES OUTLINE Introduction: Why System on Glass? MOSFET Technology Low-Temperature Poly-Si TFT Technology System-on-Glass Technology Issues Conclusion System on Glass CPU SRAM DRAM EEPROM

More information

FUNDAMENTALS OF MODERN VLSI DEVICES

FUNDAMENTALS OF MODERN VLSI DEVICES 19-13- FUNDAMENTALS OF MODERN VLSI DEVICES YUAN TAUR TAK H. MING CAMBRIDGE UNIVERSITY PRESS Physical Constants and Unit Conversions List of Symbols Preface page xi xiii xxi 1 INTRODUCTION I 1.1 Evolution

More information

Unit III FET and its Applications. 2 Marks Questions and Answers

Unit III FET and its Applications. 2 Marks Questions and Answers Unit III FET and its Applications 2 Marks Questions and Answers 1. Why do you call FET as field effect transistor? The name field effect is derived from the fact that the current is controlled by an electric

More information

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm EE241 - Spring 20 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements No office hour next Monday Extra office hour Tuesday 2-3pm 2 1 Outline

More information

FDSOI for Low Power System on Chip. M.HAOND STMicroelectronics, Crolles, France

FDSOI for Low Power System on Chip. M.HAOND STMicroelectronics, Crolles, France FDSOI for Low Power System on Chip M.HAOND STMicroelectronics, Crolles, France OUTLINE Introduction : Motivations for FDSOI FDSOI Presentation & Short Channel control MOS VT Construction Performance Analysis

More information

Notes. (Subject Code: 7EC5)

Notes. (Subject Code: 7EC5) COMPUCOM INSTITUTE OF TECHNOLOGY & MANAGEMENT, JAIPUR (DEPARTMENT OF ELECTRONICS & COMMUNICATION) Notes VLSI DESIGN NOTES (Subject Code: 7EC5) Prepared By: MANVENDRA SINGH Class: B. Tech. IV Year, VII

More information

Inspector Data Sheet. EM-FI Transient Probe. High speed pulsed EM fault injection probe for localized glitches. Riscure EM-FI Transient Probe 1/8

Inspector Data Sheet. EM-FI Transient Probe. High speed pulsed EM fault injection probe for localized glitches. Riscure EM-FI Transient Probe 1/8 Inspector Data Sheet EM-FI Transient Probe High speed pulsed EM fault injection probe for localized glitches. Riscure EM-FI Transient Probe 1/8 Introduction With increasingly challenging chip packages

More information

ESD-Transient Detection Circuit with Equivalent Capacitance-Coupling Detection Mechanism and High Efficiency of Layout Area in a 65nm CMOS Technology

ESD-Transient Detection Circuit with Equivalent Capacitance-Coupling Detection Mechanism and High Efficiency of Layout Area in a 65nm CMOS Technology ESD-Transient Detection Circuit with Equivalent Capacitance-Coupling Detection Mechanism and High Efficiency of Layout Area in a 65nm CMOS Technology Chih-Ting Yeh (1, 2) and Ming-Dou Ker (1, 3) (1) Department

More information

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor

More information

Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families

Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1 Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1. Introduction 2. Metal Oxide Semiconductor (MOS) logic 2.1. Enhancement and depletion mode 2.2. NMOS and PMOS inverter

More information

Semiconductor Devices

Semiconductor Devices Semiconductor Devices - 2014 Lecture Course Part of SS Module PY4P03 Dr. P. Stamenov School of Physics and CRANN, Trinity College, Dublin 2, Ireland Hilary Term, TCD 3 th of Feb 14 MOSFET Unmodified Channel

More information

EE5320: Analog IC Design

EE5320: Analog IC Design EE5320: Analog IC Design Handout 3: MOSFETs Saurabh Saxena & Qadeer Khan Indian Institute of Technology Madras Copyright 2018 by EE6:Integrated Circuits & Systems roup @ IIT Madras Overview Transistors

More information

Picosecond Laser Stimulation status, applications & challenges

Picosecond Laser Stimulation status, applications & challenges Picosecond Laser Stimulation status, applications & challenges Vincent POUGET IMS, University of Bordeaux, Talence, France Laboratoire de l Intégration, du Matériau au Système CNRS UMR 5218 Outline Picosecond

More information

Numerical models of MOS devices and modelling methodology of physical effects in IC substrates.

Numerical models of MOS devices and modelling methodology of physical effects in IC substrates. Numerical models of MOS devices and modelling methodology of physical effects in IC substrates. T. Krupkina, D. Rodionov, A. Nikolaev. Moscow State Institute of Electronic Technics (Technical University)

More information

SINGLE-EVENT CHARACTERIZATION OF A 90-nm BULK CMOS DIGITAL CELL LIBRARY. Nicholas M. Atkinson. Thesis. Submitted to the Faculty of the

SINGLE-EVENT CHARACTERIZATION OF A 90-nm BULK CMOS DIGITAL CELL LIBRARY. Nicholas M. Atkinson. Thesis. Submitted to the Faculty of the SINGLE-EVENT CHARACTERIZATION OF A 90-nm BULK CMOS DIGITAL CELL LIBRARY by Nicholas M. Atkinson Thesis Submitted to the Faculty of the Graduate School of Vanderbilt University in partial fulfillment of

More information

An Analytical model of the Bulk-DTMOS transistor

An Analytical model of the Bulk-DTMOS transistor Journal of Electron Devices, Vol. 8, 2010, pp. 329-338 JED [ISSN: 1682-3427 ] Journal of Electron Devices www.jeldev.org An Analytical model of the Bulk-DTMOS transistor Vandana Niranjan Indira Gandhi

More information

The Influence of the Distance between the Strike Location and the Drain on 90nm Dual-Well Bulk CMOS

The Influence of the Distance between the Strike Location and the Drain on 90nm Dual-Well Bulk CMOS International Conference on Mathematics, Modelling, Simulation and Algorithms (MMSA 8) The Influence of the Distance between the Strike Location and the Drain on 9nm Dual-Well Bulk CMOS Qiqi Wen and Wanting

More information

UNIT 3 Transistors JFET

UNIT 3 Transistors JFET UNIT 3 Transistors JFET Mosfet Definition of BJT A bipolar junction transistor is a three terminal semiconductor device consisting of two p-n junctions which is able to amplify or magnify a signal. It

More information

Integrated Circuit Amplifiers. Comparison of MOSFETs and BJTs

Integrated Circuit Amplifiers. Comparison of MOSFETs and BJTs Integrated Circuit Amplifiers Comparison of MOSFETs and BJTs 17 Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) 15 15 6 6 2.7 2.7 C ox (ff/µm 2 )

More information

PAPER SOLUTION_DECEMBER_2014_VLSI_DESIGN_ETRX_SEM_VII Prepared by Girish Gidaye

PAPER SOLUTION_DECEMBER_2014_VLSI_DESIGN_ETRX_SEM_VII Prepared by Girish Gidaye Q1a) The MOS System under External Bias Depending on the polarity and the magnitude of V G, three different operating regions can be observed for the MOS system: 1) Accumulation 2) Depletion 3) Inversion

More information

Lecture 4. MOS transistor theory

Lecture 4. MOS transistor theory Lecture 4 MOS transistor theory 1.7 Introduction: A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain is modulated by a voltage

More information

Low Power 8-Bit ALU Design Using Full Adder and Multiplexer Based on GDI Technique

Low Power 8-Bit ALU Design Using Full Adder and Multiplexer Based on GDI Technique Low Power 8-Bit ALU Design Using Full Adder and Multiplexer Based on GDI Technique Mohd Shahid M.Tech Student Al-Habeeb College of Engineering and Technology. Abstract Arithmetic logic unit (ALU) is an

More information