Improving the ability of bulk built-in current sensors to detect Single Event Effects by using triple-well CMOS

Transcription

1 ESREF th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis Improving the ability of bulk built-in current sensors to detect Single Event Effects by using triple-well CMOS J.-M. Dutertre 1, R. Possamai Bastos 2, O. Potin 3, M.L. Flottes 3, B. Rouzeyre 3, G. Di Natale 3, A. Sarafianos 4 Sept. 29 th oct. 2 nd 2014 Berlin Germany 1: ENSM.SE - Centre Microélectronique de Provence, Gardanne, France 2: TIMA Univ. Grenoble Alpes, CNRS, TIMA, F Grenoble, France 3: LIRMM (CNRS UMR N5506), Montpellier, France 4: STMicroelectronics, Rousset, France

2 Outline I. Introduction SET mechanism, BBICS principle II. Zhang et al. BBICS architecture Experimental results & unexpected weakness III. Analysis Experimental measurements Improving BBICS efficiency: use of triple-well CMOS IV. Validation A new BBICS design Simulation results 2 / 20

3 I. Introduction! Integrated circuits in radioactive environment " Suffer from various types of Single Event Effects (SEE) - Single Event Transient (SET), - Single Event Upset (SEU), - Single Event Latchup (destructive) - Single Event Gate Rupture, etc.! Bulk Built-In Current Sensor (BBICS) " Design to monitor the advent of SETs and SEUs " Not to prevent their effects 3 / 20

4 I. Introduction! SET mechanism The inverter case in 0 Metal 1 MOS gate out 1 C " to Gnd to Vdd N+ N+ N+ PTAP NMOS sensitive PN junction PMOS N well Sensitive area: reverse biased PN junction (drain of the off transistor) 4 / 20

5 I. Introduction! SET mechanism The inverter case ionizing ion track in 0 Metal 1 MOS gate out 1 C " to Gnd to Vdd N+ N+ N+ PTAP NMOS PMOS N well Sensitive area: reverse biased PN junction (drain of the off transistor) 4 / 20

6 I. Introduction! SET mechanism The inverter case ionizing ion track in 0 Metal 1 MOS gate out 1 => 0 C " to Gnd to Vdd N+ N+ N+ PTAP NMOS PMOS N well SEE current flows through substrate and its biasing TAPs 4 / 20

7 I. Introduction! BBICS principle: monitoring bulk currents in 0 Metal 1 MOS gate out 1 C " to Gnd to Vdd N+ N+ N+ PTAP NMOS PMOS N well SEE current flows through substrate and its biasing TAPs 5 / 20

8 I. Introduction! BBICS principle: monitoring bulk currents to Gnd in 0 Metal 1 MOS gate BBICS out 1 C " NMOS_bulk to Vdd N+ N+ N+ PTAP NMOS PMOS N well BBICS: monitor SEE current through node NMOS_bulk 5 / 20

9 I. Introduction! BBICS principle: monitoring bulk currents to Gnd in 0 Metal 1 MOS gate BBICS out 1 C " NMOS_bulk to Vdd N+ N+ N+ PTAP NMOS PMOS N well BBICS: monitor SEE current through node NMOS_bulk 5 / 20

10 I. Introduction! BBICS principle: monitoring bulk currents to Gnd alarm flag in 0 Metal 1 MOS gate BBICS out 1 C " NMOS_bulk to Vdd N+ N+ N+ NTAP NMOS PMOS N well BBICS: monitor SEE current through node NMOS_bulk 5 / 20

11 II. Zhang et al. BBICS architecture! Zhang et al. BBICS architecture [zhang2010] " Published in 2010, experimental validation reported in 2013 NMOS monitoring less effective than expected?! Vdd reset Tr Vdd NMOS_bulk 1 => 0 T1 outn_bar outn T3 0 => 1 NMOS_bulk Vdd T2 Gnd NMOS-BVIS Gnd 6 / 20

12 II. Zhang et al. BBICS architecture " NMOS-BVIS : NMOS monitoring / PMOS-BVIS : PMOS monitoring Vdd reset Tr Vdd NMOS_bulk 1 => 0 T1 outn_bar outn T3 0 => 1 NMOS_bulk Vdd T2 Gnd NMOS-BVIS Gnd N+ N+ N+ PMOS_bulk PMOS-BVIS NMOS PMOS N well 7 / 20

13 II. Zhang et al. BBICS architecture " Experimental testing of NMOS-/PMOS-BVIS [zhang2013] Test chip CMOS bulk 90 nm: many instances of NMOS-/PMOS-BVIS, multiplier as a test element. PMOS-BVIS NMOS-BVIS PMOS-BVIS NMOS-BVIS vdd NTAP biasing PTAP biasing multiplier std cells gnd 8 / 20

14 II. Zhang et al. BBICS architecture " Experimental testing of NMOS-/PMOS-BVIS [zhang2013] Ionizing particle effect emulation with a laser source: - λ = 800 nm, laser spot Ø = 1.6 µm, pulse duration = 1 ps # of biasing contact (NTAPs or PTAPs) Multiplier SEE sensitivity threshold 82 pj 82 pj 82 pj 82 pj PMOS-BVIS detection threshold 15 pj 42 pj 75 pj n.d. NMOS-BVIS detection threshold 110 pj 149 pj n.d. n.d. n.d. = not detected PMOS monitoring: efficient up to 80 biasing contacts NMOS monitoring: inefficient SEE sensitivity always < BBICS detection threshold 9 / 20

15 III. Analysis! Experimental measurements " Understanding SEE currents in NMOS/PMOS Test chip: CMOS 90 nm, bulk and triple-well, single NMOS and PMOS Experiment settings: measure of laser-induced currents at λ = 1064 nm, laser spot Ø = 5 µm, pulse duration = 20 µs, 1.25 W (settings outside ionizing particle emulation) EMSE laser facility 10 / 20

16 ! Experimental measurements " Understanding SEE currents in NMOS/PMOS III. Analysis Test chip: CMOS 90 nm, bulk and triple-well, single NMOS and PMOS Experiment settings: measure of laser-induced currents at λ = 1064 nm, laser spot Ø = 5 µm, pulse duration = 20 µs, 1.25 W (settings outside ionizing particle emulation) NMOS current: B (gnd) D (1.2V) G S 2.5 ma N+ N+ NMOS laser beam 10 / 20

17 III. Analysis PMOS current: Psub bias (floating) S G D (gnd) B (1.2V) N+ Psub-Nwell junction unbiased PMOS 1.9 ma N well laser beam Psub bias (gnd) S G D (gnd) B (1.2V) Psub-Nwell junction reverse biased N+ PMOS 200 µa 8 ma N well laser beam 11 / 20

18 III. Analysis Analysis: Bulk current an order of magnitude above drain current Promote detection over SEE generation Drain current contributing to SEE 200 µa Psub bias (gnd) S Bulk current (PMOS-BBICS monitored) 8 ma G D (gnd) B (1.2V) N+ PMOS 200 µa 8 ma laser beam N well 12 / 20

19 III. Analysis! Improving BBICS efficiency " Use of triple-well CMOS NMOS in Pwell to mimic PMOS properties G S D (1.2V) B (gnd) DNwell bias (1.2V) Nwell N+ N+ NMOS Pwell DNwell (grounded) N+ Nwell 13 / 20

20 III. Analysis! Improving BBICS efficiency " Use of triple-well CMOS NMOS in Pwell to mimic PMOS properties NMOS current: G S D (1.2V) B (gnd) DNwell bias (floating) Nwell N+ N+ NMOS 2.3 ma DNwell Pwell N+ Nwell Pwell-DNwell junction unbiased laser beam 13 / 20

21 " Use of triple-well CMOS Pwell-DNwell junction NMOS current: reverse biased Drain current contributing to SEE 200 µa G S D (1.2V) B (gnd) DNwell bias (1.2V) III. Analysis Bulk current (NMOS-BBICS monitored) 6 ma Nwell N+ N+ NMOS Pwell DNwell laser beam 200 µa 6 ma N+ Nwell Bulk current an order of magnitude above drain current Promote detection over SEE generation 14 / 20

22 ! Single BBICS architecture Design of a test chip: CMOS 65-nm (bulk and triple-well) IV. Validation New BBICS architecture: the single BBICS (design to bring together NMOS and PMOS monitoring ability) to PMOS bulk reset HVT HVT NMOS_bulk Vdd out_d Mn4 Gnd Mn_reset Gnd to NMOS bulk LVT Mn3 Gnd outb LVT HVT Vdd Mn1 Gnd 1 => 0 Mp1 Mn_t Vdd out_d outb_d Gnd Mp_t Vdd Mp2 Mn2 Gnd HVT LVT out Vdd Mp3 0 => 1 resetb LVT Vdd Mp4 HVT HVT Gnd PMOS_bulk Vdd Mp_reset outb_d 15 / 20

23 IV. Validation " Validation on the basis of simulation Post-layout electrical simulation (parasitic R and C extracted) Current source to model SEE currents: current pulse, double exponent, 50 ps rise time, 150 ps fall time, µa range Investigation of SEE and BBICS detection thresholds PMOS_bulk single BBICS MOS_bulk 40 inverters 40 inverters 16 / 20

24 IV. Validation " Validation on the basis of simulation 1. CMOS bulk (NMOS on Psub, ie. no triple-well) # of inverters Threshold of NMOS SET 102 µa 104 µa 104 µa 104 µa Single BBICS detection threshold 56 µa 82 µa 107 µa 155 µa Threshold of PMOS SET 126 µa 131 µa 134 µa 137 µa corresp. PMOS bulk current >1.2mA >1.3mA >1.3mA >1.3mA Single BBICS detection threshold 45 µa 67 µa 107 µa 134 µa NMOS monitoring weakness confirmed on the basis of simulation 17 / 20

25 IV. Validation " Validation on the basis of simulation 2. Triple-well CMOS (NMOS in Pwell) # of inverters Threshold of NMOS SET 94 µa 95 µa 98 µa 100 µa corresp. NMOS bulk current >0.9mA >0.9mA >0.9mA >1 ma Single BBICS detection threshold 75 µa 112 µa 147 µa 212 µa Threshold of PMOS SET 118 µa 125 µa 127 µa 130 µa corresp. PMOS bulk current >1.1mA >1.2mA >1.2mA >1.3mA Single BBICS detection threshold 84 µa 125 µa 163 µa 237 µa Triple-well restore NMOS monitoring ability of BBICS 18 / 20

26 IV. Conclusion! Review of BBICS principle " Exp. revealed a weakness in monitoring NMOS! Analysis and proposal of a solution " Use of triple-well CMOS (NMOS in Pwells) " Validation on simulation basis (new BBICS architecture)! Perspectives " Experiments on a CMOS 65-nm test chip 19 / 20

27 Thank you for your attention [zhang2010], Zhang et al., CCECE 2010 A new bulk built-in current sensing circuit for single-event transient detection [zhang2013], Zhang et al., Journal of electronic testing 2013 A Bulk Built-In Voltage Sensor to Detect Physical Location of Single-Event Transients 20 / 20