EE5320: Analog IC Design

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1 EE5320: Analog IC Design Handout 3: MOSFETs Saurabh Saxena & Qadeer Khan Indian Institute of Technology Madras Copyright 2018 by EE6:Integrated Circuits & Systems IIT Madras

2 Overview Transistors in CMOS technology Focus on NMOS and PMOS Derive I/V characteristics Regions of operation Small-signal model Secondary effects: channel-length modulation, body effect Extrinsic capacitors References 1. Y. Tsividis, Operation and Modeling of the MOS Transistor, Oxford University Press, 2006 S. Saxena & Q. Khan EE5320: HO#3 2

3 Contact Terminals in NMOS Transistor B S D 0.25µm 700µm 4nm p+ 0.18µm p-substrate (10 W-cm) D: Drain : ate S: Source B: Bulk/substrate D S B No current with zero bias voltages for /D/S/B S. Saxena & Q. Khan EE5320: HO#3 3

4 Channel Formation: Depletion B S V D Depletion region p+ p-substrate Small positive voltage on the gate terminal introduces electric field in the p-substrate Holes in the p-substrate are repelled leaving negative ions Forming depletion region Larger gate voltage increases depletion width S. Saxena & Q. Khan EE5320: HO#3 4

5 Channel Formation: Inversion B S V D Inversion region p+ p-substrate Larger gate voltage pulls electrons from electron-rich source/drain region inverting majority carriers near gate Electron rich source (), drain (), & inverted substrate near gate forms a channel of free electron carriers S. Saxena & Q. Khan EE5320: HO#3 5

6 Channel Conduction B S V D V D p+ p-substrate Apply positive voltage on the drain terminal creating potential difference between drain and source Electrons flow from source to drain Current flows form drain to source Larger gate voltage increases drain-to-source current S. Saxena & Q. Khan EE5320: HO#3 6

7 Threshold Voltage Formation of a channel (inversion layer) is gradual Need a voltage to indicate channel formation Threshold voltage: ate-to-source voltage to invert the surface of the substrate with same doping density For an NMOS, it is the voltage to make the surface n-type as much as the substrate is p-type V TH 0.5V in 0.18 m process S. Saxena & Q. Khan EE5320: HO#3 7

8 Channel Resistance S V D L x V V -V D V D ate to Channel Potential V V -V D Channel Potential x 0 (source) L (drain) Channel can be modeled as a resistor For positive drain voltage: Channel potential decreases from drain to source (IR drop) ate-to-channel potential increases from drain to source S. Saxena & Q. Khan EE5320: HO#3 8

9 Channel Pinch-off B S V D V D p+ p-substrate If V TH > V -V D inversion layer stops at x L Channel is said to be pinched-off Carriers drift as opposed to diffusion Channel current saturates Increasing V DS does not increase I DS provided V < V D +V TH Channel length modulated by V DS Large V DS Smaller channel length S. Saxena & Q. Khan EE5320: HO#3 9

10 NMOS Channel Current Equation(1) B S V D V D p+ p-substrate 0 L x S. Saxena & Q. Khan EE5320: HO#3 10

11 NMOS Channel Current Equation(2) During pinch-off, channel ceases to exist at drain At pinch-off point, V DS =V S -V TH S. Saxena & Q. Khan EE5320: HO#3 11

12 NMOS I/V Characteristics I DS 0 V S3 >V S2 >V S1 >V TH Triode V SX -V TH V S3 V S2 V S1 Saturation V DS For conduction, V S > V TH In triode region, drain current is dependent on V DS In saturation region, drain current is independent on V DS S. Saxena & Q. Khan EE5320: HO#3 12

13 NMOS Regions of Operation Notation : V S V TH = V OV = Overdrive voltage S. Saxena & Q. Khan EE5320: HO#3 13

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