KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 6 FIELD-EFFECT TRANSISTORS

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1 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 1 6 FIELD-EFFECT TRANSISTORS Most of the content is from the textbook: Electronic devices and circuit theory, Robert L. Boylestad, Louis Nashelsky, 11th ed, 2013

2 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept Introduction BJT: Bipolar device Holes and electrons as carriers Current controlled Typical ac voltage gains for BJT amplifiers are more than for FETs. FET: Unipolar device Just holes ( p-channel) or electrons (n-channel) Voltage controlled Smaller More temperature stability High input impedance (1 M ) JFET: Junction FET MOSFET : Metal Oxide Semiconductor FET CMOS : Complementary Metal Oxide Semiconductor (or Complementary MOSFET arrangement) MESFET : Metal Semiconductor FET The field-effect transistor (FET) is a three-terminal device used for a variety of applications that match, to a large extent, those of the BJT transistor. The BJT transistor is a current-controlled device whereas the JFET transistor is a voltage-controlled device

3 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept JFETs Why do we use the term field effect? We are all familiar with the ability of a permanent magnet to draw metal filings to itself without the need for actual contact. The magnetic field of the permanent magnet envelopes the filings and attracts them to the magnet along the shortest path provided by the magnetic flux lines. For the FET an electric field is established by the charges present, which controls the conduction path of the output circuit without the need for direct contact between the controlling and controlled quantities. Three-terminal device with one terminal capable of controlling other two. Major part is the n-channel which forms the channel between the embedded layers of p -type material. The top of the n -type channel is connected through an ohmic contact to a terminal referred to as the drain (D), whereas the lower end of the same material is connected through an ohmic contact to a terminal referred to as the source (S). The two p type materials are connected together and to the gate (G) terminal No-bias condition depletion region is fixed. (n-channel JFET)

4 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 4 Analogies are seldom perfect and at times can be misleading, but the water analogy of provide a sense for the JFET control at the gate terminal and the appropriateness of the terminology applied to the terminals of the device. The source of water pressure can be likened to the applied voltage from drain to source, which establishes a flow of water (electrons) from the source. The gate, through an applied signal (potential), controls the flow of water (charge) to the drain. V GS = 0 V, V DS Some Positive Value The instant the voltage V DD (V DS ) is applied, the electrons are drawn to the drain terminal, establishing the conventional current I D. The path of charge flow clearly reveals that the drain and source currents are equivalent (I D = I S ). The flow of charge is relatively uninhibited and is limited solely by the resistance of the n -channel between drain and source.

5 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 5 The current I D will establish the voltage levels through the channel as indicated on the same figure. The result is that the upper region of the p -type material will be reverse-biased by about 1.5 V, with the lower region only reverse-biased by 0.5 V. Recall from the discussion of the diode operation that the greater the applied reverse bias, the wider is the depletion region. V P As the voltage V DS is increased from 0 V to a few volts, the current will increase as determined by Ohm s law and the plot of I D versus V DS will appear as shown in the figure. The relative straightness of the plot reveals that for the region of low values of V DS, the resistance is essentially constant. As V DS increases and approaches a level referred to as V P, the depletion regions will widen, causing a noticeable reduction in the channel width. The reduced path of conduction causes the resistance to increase and the curve in the graph to occur. The more horizontal the curve, the higher the resistance, suggesting that the resistance is approaching infinite ohms in the horizontal region. If V DS is increased to a level where it appears that the two depletion regions would touch as shown in, a condition referred to as pinch-off will result.

6 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 6 In essence, therefore, once V DS > V P the JFET has the, the current is fixed at I D = I DSS, but the voltage V DS (for levels > V P ) is determined by the applied load. V GS = V P The choice of notation I DSS is derived from the fact that it is the drain-to-source current with a short-circuit connection from gate to source. As we continue to investigate the characteristics of the device we will find that: I DSS is the maximum drain current for a JFET. For all levels of V GS between 0 V and the pinch-off level, the current I D will range between I DSS and 0 A, V GS = V P

7 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 7 V GS < 0 V The effect of the applied negative-bias V GS is to establish depletion regions similar to those obtained with V GS = 0V, but at lower levels of V DS. Therefore, the result of applying a negative bias to the gate is to reach the saturation level at a lower level of V DS The resulting saturation level for I D has been reduced and in fact will continue to decrease as V GS is made more and more negative. Pinch-off voltage continues to drop in a parabolic manner as V GS becomes more and more negative. Eventually, when V GS = V P the device has been turned off.

8 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 8 The region to the left of the pinch-off locus is referred to as the ohmic or voltage-controlled resistance region. In this region the JFET can actually be employed as a variable resistor (possibly for an automatic gain control system) whose resistance is controlled by the applied gate-to-source voltage. For Ohmic region r d = 1 V 2 GS V P r o : Resistance when V GS = 0 e.g: for V GS = 3 V, V P = 6 V, r o = 10 k r d = 40 k for V GS = 6 V, with V P = 6 V, I D = 0 JFET will be in the cut-off region. r o

9 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 9 Transfer Characteristics I C = f I B = βi B β constant, I B control variable I D = I DSS 1 V GS V P I DSS, V P constants,v GS control variable 2 Nonlinear relationship between I D and V GS producing a curve that grows exponentially with decreasing magnitude of V GS. If a horizontal line is drawn from the V GS = 1 V curve to the I D axis and then extended to the other axis, another point on the transfer curve can be located. Note that Note in the definition of I D at V GS = 0 V and 1 V that the saturation levels of I D are employed and the ohmic region ignored. Continuing with V GS = 2 V and 3 V, we can complete the transfer curve.

10 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 10 Recall that V BE = 0.7 V was often the key to initiating an analysis of a BJT configuration. Similarly, the condition I G = 0 A is often the starting point for the analysis of a JFET configuration. For the BJT configuration, I B is normally the first parameter to be determined. For the JFET, it is normally V GS.

11 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept Depletion-type MOSFET MOSFETs are further broken down into depletion type and enhancement type. SiO 2 layer is an insulating layer. There is no direct electrical connection between the gate terminal and the channel of a MOSFET. It is the insulating layer of SiO 2 in the MOSFET construction that accounts for the very desirable high input impedance of the device. Thus MOSFET has higher input impedance than that of JFET

12 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 12 Basic Operation and Characteristics V GS = 0, V DS > 0 Free e flows along the channel. V GS < 0, V DS > 0 When applied a negative V GS the potential at gate attracts holes of p, repels e of n to p. This reduces e available for conduction in the channel. More negative bias less drain current Limit is the pinch off level (e.g. 6 V)

13 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 13 V GS > 0, V DS > 0 When applied a positive V GS the potential at gate attract additional e from p, repels holes of n to p. This increases e available for conduction in the channel. More positive bias more drain current. The application of a positive gate-to-source voltage has enhanced the level of free carriers in the channel compared to that encountered with V GS = 0 V. For this reason the region of positive gate voltages on the drain or transfer characteristics is often referred to as the enhancement region. I D = I DSS e.g: for I DSS = 8mA V GS = 1 V V P = 6 V, I D = 10.9 ma 1 V GS V P 2

14 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept Enhancement-type MOSFET Although there are some similarities in construction and mode of operation between depletion type and enhancement-type MOSFETs, the characteristics of the enhancement-type MOSFET are quite different from anything obtained thus far. The transfer curve is not defined by Shockley s equation, and the drain current is now cut off until the gate-to source voltage reaches a specific magnitude. In particular, current control in an n channel device is now effected by a positive gate-to-source voltage rather than the range of negative voltages encountered for n -channel JFETs and n -channel depletion-type MOSFETs. There is no channel between the two n -doped regions. This is the primary difference between the construction of depletion-type and enhancement-type MOSFETs The SiO 2 layer is still present to isolate the gate metallic platform from the region between the drain and source, but now it is simply separated from a section of the p - type material

15 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 15 Basic Operation and Characteristics V GS = 0, V DS = 0 No channel. V GS = 0, V DS > 0 No channel again. V GS > 0, V DS > 0 When applied a positive V GS the potential at gate attracts e of p Insulator again ensures e is not absorbed at gate. Level of V GS for significant I D increase is the V T (V T > 0). An enhanced channel is created.

16 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 16 However, if we hold V GS constant and increase the level of V DS, the drain current will eventually reach a saturation level as occurred for the JFET and depletion-type MOSFET. The leveling off of I D is due to a pinching-off process depicted by the narrower channel at the drain end of the induced channel. For values of V GS less than the threshold level, the drain current of an enhancement type MOSFET is 0 ma. V DSsat = V GS V T

17 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 17 For V GS > V T the drain current is related to the applied gate-to-source voltage by the following nonlinear relationship: 2 I D = k V GS V T I D (on) k = (V GS on V T ) 2 k constant special for device, can be determined. I D (on), V GS on particular point on the characteristics of the device. e.g: I D on = 10 ma V GS on = 8 V V T = 2 V k x 10 3 A/V 2 I D = x V GS V T

18 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept. 18

19 KOM2751 Analog Electronics :: Dr. Muharrem Mercimek :: YTU - Control and Automation Dept CMOS A very effective logic circuit can be established by constructing a p -channel and an n channel MOSFET on the same substrate. Note the induced p -channel on the left and the induced n -channel on the right for the p - and n - channel devices, respectively. The configuration is referred to as a complementary MOSFET arrangement (CMOS); it has extensive applications in computer logic design. The relatively high input impedance, fast switching speeds, and lower operating power levels of the CMOS configuration have resulted in a whole new discipline referred to as CMOS logic design.

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