KOREA UNIVERSITY. Photonics Laboratory. Ch 15. Field effect Introduction-The J-FET and MESFET

Transcription

1 Ch 15. Field effect Introduction-The J-FET and MESFET : (a) The device worked on the principle that a voltage applied to the metallic plate modulated the conductance of the underlying semiconductor, which in turn modulated the current flowing between ohmic contacts A and B. This phenomenon, where the conductivity of a semiconductor is modulated by an electric field applied normal to the surface of the semiconductor, has been named the field effect. (b) A key component of present-day microelectronics, the metal-oxide-semiconductor field effect transistor (MOSFET), achieved practical status during the early 1960s. The structure with thermally grown SiO 2 functioning as the gate insulator, a surface-inversion channel, and islands doped opposite to the substrate acting as the source and drain was first reported by Kahng and Atalla in 1960: 1

2 1. General Introduction 1. General Introduction 1) Like bipolar junction transistor, junction field effect transistor JFET is also a threeterminal device but it is a unipolar device, which shall mean that the current is made of either electron or hole carrier. 2) The operation of JFET is controlled by electric field effect. Thus, JFET is a voltagecontrolled current source device, whereas BJT is a current-controlled source device. 3) There are two types of JFET namely n-channel and p-channel. n-channel type means the carrier type in the conducting channel is electron. Likewise, for p-channel type, the carrier type in conducting channel is hole. 4) JFET has three terminals, which are gate G, drain D and source S. The gate is used to control the flow of carrier from source to drain. Source is the terminal that emits carrier and the drain is the terminal that receives carrier. 2

3 JFET: The structures of n-channel and p-channel JFETs are shown (a) n-channel JFET (b) p-channel JFET The structures of n-channel and p-channel 3

4 JFET: The symbols of n-channel and p-channel JFETs (a) n-channel JFET (b) p-channel JFET Symbols of n-channel and p-channel JFET 4

5 2. JEFT 5

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11 J-FET 11

12 2. Biasing the JFET 3. Biasing the JFET 1) In normal operation, the gate of JFET is always reverse-biased. Thus, an n-channel type, the gate is biased with negative voltage i.e. gate voltage is less than zero volt V G < 0, whilst for p-channel type, the gate is biased with positive voltage i.e. gate voltage is greater than zero voltage V G > 0. 2) The source and drain are biased according to the channel type or carrier type. If it is an n-channel JFET (electron as carrier), the source is biased with negative voltage while the drain is biased with positive voltage. Alternatively, it can be biased such that the drain voltage V D is greater than the source voltage V S. i.e. V D > V S. 3) If it is a p-channel JFET (hole as carrier), the source is biased with positive voltage while the drain is biased with negative voltage. Alternatively, it can be biased such that the drain voltage V D is less than the source voltage V S. i.e. V D < V S. 12

13 2. Biasing the JFET : (a) The depletion regions extend primarily into the lightly doped n-region of the device. When stepping V D to small positive voltages, a current, I D, begins to flow into the drain and through the nondepleted n-region sandwiched between the two p + -n junctions, where the nondepleted current-carrying region is referred to as the channel. For small V D, the channel looks and acts like a simple resistor and the resulting variation of I D with V D is linear. (b) When V D is increased above a few tenths of a volt, the device typically enters a new phase of operation. Since the source is grounded, it naturally follows that somewhere in the channel the potential takes on the gradual changes of voltage, with the potential increasing as one progresses from the source to the drain. (c) consequently, the applied drain bias leads indirectly to a reverse biasing of the gate junctions and an increase in the junction depletion widths. Moreover, the top and bottom depletion regions progressively widen in going down the channel from the source to the drain. 13

14 2. Biasing the JFET (d) Still thinking of the channel region as a resistor, but no longer a simple resistor, one would expect the loss of conductive volume to increase the source-to-drain resistance and reduce the ΔI D resulting from a given change in drain voltage. The slope of the I D -V D characteristic decreases at larger drain biases because of the channel-narrowing effect. (e) Continuing to increase the drain voltage obviously causes the channel to narrow more and more, especially near the drain, until eventually the top and bottom depletion regions touch in the near vicinity of the drain. The complete depletion of the chnnel is an important special condition and is referred to as pinch-off. When the channel pinches off inside the device, the solpe of the I D -V D characteristic becomes approximately zero, and the drain bias at the pinch-off point is given the special designation V Dsat. 14

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17 4. I-V characteristics B C A 17

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