Electronics I. Last Time
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1 (Rev. 1.0) Electronics I Lecture 28 Introduction to Field Effect Transistors (FET s) Muhammad Tilal Department of Electrical Engineering CIIT Attock Campus The logo and is the property of CIIT, Pakistan and subject to the copyrights and ownership of. Duplication & distribution of this work for Non Academic or Commercial use without prior permission is prohibited. The theme of this presentation is an inspiration from the one used in S2 Department of Chalmers University of Technology, Gothenburg, Sweden. Last Time BJT Design Operations. Fixed Bias Configuration. Emitter Stabilized Bias Configuration. Voltage Divider Bias Configuration. Concepts Determination of Collector Resistance, RC. Determination of Emitter Resistance, RE. Determination of Base Resistance, RC/R1/R2. 10/4/2013 Muhammad Tilal 2 1
2 Session Overview Topic Concepts Recommended Reading Keywords Introduction to FET s. BJT vs FET, FET Types, FET Construction, FET Operation, Pinch off. Sections?? Of [1] FET, BJT, Current Controlled, Voltage controlled, JFET, MOSFET, Gate, Source, Drain, Pinch off. 10/4/2013 Muhammad Tilal 3 BJT Vs FET (1) BJT is a current controlled device Base current (IB) controls the collector current (IC). This implies IC is a direct function of IB. FET is a voltage controlled device. Gate to Source voltage (VGS) controls the current I. This implies I is a direct function of VGS. BJT is a bipolar device Both electrons and holes constitute the current. FET is a uni-polar device. Only electrons (n- channel) or only holes(pchannel) constitute the current. Bipolar Unipolar Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 4 2
3 BJT Vs FET (2) BJT Low Input Impedance. More sensitive to the changes in the applied signal. Change in output with input change is greater. Less temperature stability. Larger in size FET High Input Impedance. Important for linear ac amp design. Less sensitive to the changes in the applied signal. More temperature stable. Better suited in temperature sensitive applications. Smaller in size. Better for IC manufacturing. 10/4/2013 Muhammad Tilal 5 Classification of FET s FET MOSFET JFET Enhancement Type Depletion Type FET: Field Effect Transistor. MOSFET: Metal Oxide Semiconductor Field Effect Transistor. JFET: Junction Field Effect Transistor. 10/4/2013 Muhammad Tilal 6 3
4 JFET Structure Figure shows an n channel JFET. Upper end is Drain. Lower end is Source. The p type regions are connected together and called as Gate. For p channel JFET, the terminals remain same but the n and p type materials replace each other. JFET Structural Diagram JFET Schematic Diagram Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 7 Basic Operation VDD provides Drain to source voltage. Current from drain to source. VGS sets The reverse bias voltage between the gate and the source. In JFET operation The gate- source pn junction is always reverse biased. This reverse biasing produces a depletion region along the pn junction. This depletion region extends to n channel and channel width & resistance are increased. Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 8 4
5 Operating Conditions for JFET Three basic operating conditions for a JFET VGS= 0, VDS at some positive value. VGS < 0, VDS at some positive value. Voltage controlled resistor. For n channel JFET VGS may never be positive. For p- channel JFET VGS may never be negative. 10/4/2013 Muhammad Tilal 9 JFET Characteristics and Parameters When VGS = 0V and VDD is increased from 0 to more positive value The depletion region between p- gate and n- channel increases as electrons from n- channel combine with holes from p- gate. Increasing the depletion region decreases the size of the n- channel which increases the resistance of the n- channel. Even though n- channel resistance is increasing, the current ID from source to drain from n- channel is increasing because VDS is increasing. Robert L. Boylestad, Electronic Devices and Circuit Theory, 8 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 10 5
6 Pinch Off If VGS= 0 and VDS is further increased to more positive voltage, then the depletion zone becomes so large that it pinches off the n- channel. The current ID should drop to 0A but it shows an opposite behavior- ID increase with increasing VDS. Robert L. Boylestad, Electronic Devices and Circuit Theory, 8 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 11 Saturation At pinch off point Any further increase in VGS does not produce an increase in ID. VDS at pinch off is denoted as Vp. ID is at saturation or maximum and denoted as IDSS. The ohmic value of the channel is maximum. Robert L. Boylestad, Electronic Devices and Circuit Theory, 8 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 12 6
7 VGS < 0V As VGS becomes more negative Depletion region increases. The JFET experiences pinch off voltage at a lower voltage. ID decreases (ID<IDSS) even though VDS is increased. Eventually ID reaches 0A. VGS at this point is called VP or VGS (off). At high levels of VDS, the JFET reaches a breakdown situation. ID increases uncontrollably if VDS > VDSmax. Robert L. Boylestad, Electronic Devices and Circuit Theory, 8 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 13 VGS < 0V Robert L. Boylestad, Electronic Devices and Circuit Theory, 8 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 14 7
8 Voltage Controlled Resistor The region to the left of the pinch off is called Ohmic region. The JFET can be used as a variable resistor where VGS controls the drain-source resistance (rd). AS VGS becomes more negative, rd increases Robert L. Boylestad, Electronic Devices and Circuit Theory, 8 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 15 References [1] Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7 th Edition, Pearson Education Inc, ISBN: [2] Robert L. Boylestad, Electronic Devices and Circuit Theory, 8 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 16 8
9 (Rev. 1.0) Electronics I Lecture 29 JFET s Transfer Characteristics Muhammad Tilal Department of Electrical Engineering CIIT Attock Campus The logo and is the property of CIIT, Pakistan and subject to the copyrights and ownership of. Duplication & distribution of this work for Non Academic or Commercial use without prior permission is prohibited. The theme of this presentation is an inspiration from the one used in S2 Department of Chalmers University of Technology, Gothenburg, Sweden. Last Time Introduction to FETs. Comparison with BJT. Classification of FETs. Structure of JFET s. Operation of JFET. 10/4/2013 Muhammad Tilal 2 1
10 Session Overview Topic Concepts Recommended Reading Keywords JFET Transfer Characteristics and DC Biasing. Shockley s Equation, Transfer Curve, Shockley s Equation, FET DC Biasing. Section(s)?? of [1] Section(s)?? of [2] Application of JFET, Shockley, Gate, Source, Drain, Pinch off, VGS. 10/4/2013 Muhammad Tilal 3 Transfer Characteristics For BJTs IB and IC are related by β IC = β IB. It is a linear relationship where β is constant. For JFET the transfer characteristics of input to output is not a linear and straightforward function. In JFET, VGS and ID are related by Where ID = Drain current. IDSS = Maximum drain current. VGS= Gate to source voltage. Vp = Pinch off voltage. 10/4/2013 Muhammad Tilal 4 2
11 Transfer Curve There are two approaches to be applied for the DC analysis. Graphical. Mathematical. Graphical approach is more direct and easier in terms of application. For graphical approach, two plots are required Device characteristics plot. Network equation plot. The transfer characteristics defined by Shockley s equation are unaffected by the network in which the device is employed. 10/4/2013 Muhammad Tilal 5 Transfer Curve Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 6 3
12 Shockley s Equation (Application) The transfer curve can be obtained directly from Shockley s equation 10/4/2013 Muhammad Tilal 7 Shorthand Method (Shockley s Eq) The transfer curve can be obtained directly from Shockley s equation 10/4/2013 Muhammad Tilal 8 4
13 Example Example 5-1 (Boylestad): Sketch the transfer curve defined by IDSS = 12 ma and Vp = -6V. 10/4/2013 Muhammad Tilal 9 Example Example 5-2 (Boylestad): Sketch the transfer curve for a p channel device with IDSS = 4 ma and Vp = 3V. 10/4/2013 Muhammad Tilal 10 5
14 DC Biasing (Fixed Bias Confg) Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 11 Fixed Bias Configuration Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 12 6
15 Fixed Bias Configuration Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 13 Shockley Equation Plot Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 14 7
16 Graphical Solution Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 15 Example Example 6-1 (Boylestad): Determine VGSQ, IDQ, VDS, VD, VG, VS for the given network. Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 16 8
17 References [1] Thomas L. Floyd, Electronic Devices (Conventional Current Version), 7 th Edition, Pearson Education Inc, ISBN: [2] Robert L. Boylestad, Electronic Devices and Circuit Theory, 8 th Edition, Pearson Education Inc, ISBN: /4/2013 Muhammad Tilal 17 9
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