EDC UNIT IV- Transistor and FET JFET Characteristics EDC Lesson 4- ", Raj Kamal, 1

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1 EDC UNIT IV- Transistor and FET Characteristics Lesson-10: JFET Characteristics Qualitative Discussion 2008 EDC Lesson 4- ", Raj Kamal, 1

2 n-junction FET and p-jfet Symbols D D + D G + V DS V DS V GS S + S V GS G 2008 EDC Lesson 4- ", Raj Kamal, 2

3 N channel JFET structure 2008 EDC Lesson 4- ", Raj Kamal, 3

4 Functioning of JFET The gate is connected to the source. Since the pn junction is reversebiased, little current will flow in the gate connection. The potential gradient established will form a depletion layer, where almost all the electrons present in the n-type channel will be swept away. The most depleted portion is in the high field between the G and the D, and the least-depleted area is between the G and the S EDC Lesson 4- ", Raj Kamal, 4

5 Case 1: V GS = 0 V and V DS some +ve value at Junction Field Effect Transistor (JFET) 2008 EDC Lesson 4- ", Raj Kamal, 5

6 JFET Functioning Because the flow of current along the channel from the (+ve) drain to the (-ve) source is really a flow of free electrons from S to D in the n-type Si, the magnitude of this current will fall as more Si becomes depleted of free electrons. There is a limit to the drain current (I D ) which increased V DS can drive through the channel. This limiting current is known as I DSS (Drain-to-Source current with the gate shorted to the source) EDC Lesson 4- ", Raj Kamal, 6

7 Output characteristics of an n-channel JFET with the gate short-circuited to the source V GS = EDC Lesson 4- ", Raj Kamal, 7

8 Output characteristics of an n-channel JFET with the gate short-circuited to the source The initial rise in I D is related to the buildup of the depletion layer as V DS increases. The curve approaches the level of the limiting current I DSS when I D begins to be pinched off. The physical meaning of this term leads to one definition of pinch-off voltage, V P, which is the value of V DS at which the maximum I DSS flows EDC Lesson 4- ", Raj Kamal, 8

9 2008 EDC Lesson 4- ", Raj Kamal, 9

10 Increasing V DS increases the widths of depletion layers, which penetrate more into channel and hence result in more channel narrowing toward the drain. The resistance of the n-channel, R AB therefore increases with V DS. The drain current: I DS = V DS /R AB 2008 EDC Lesson 4- ", Raj Kamal, 10

11 I D versus V DS exhibits a sublinear behavior, see figure for V DS < 5V. The pinch-off voltage, V P is the magnitude of reverse bias needed across the p + n junction to make them just touch at the drain end. Since actual bias voltage across p + n junction at drain end is V GD, the pinch-off occur whenever: V GD = V P EDC Lesson 4- ", Raj Kamal, 11

12 Beyond V DS = V P, there is a short pinch-off channel of length, l po. As V DS increases, most of additional voltage simply drops across l po as this region is depleted of carriers and hence highly resistive. Voltage drop across channel length, L ch remain as V P. Beyond pinch-off then I D = V P /R AP (V DS >V P ) EDC Lesson 4- ", Raj Kamal, 12

13 Case 2: V GS 0 V and V DS some +ve value at Junction Field Effect Transistor (JFET) 2008 EDC Lesson 4- ", Raj Kamal, 13

14 Output characteristics of an n-channel JFET With a steady gate-source voltage of 1 V There is always 1 V across the wall of the channel at the source end. A drain-source voltage of 1 V means that there will be 2 V across the wall at the drain end. The higher voltage difference at the drain end means that the electron channel is squeezed down a bit more at this end (reduced channel, higher resistance to current flow) 2008 EDC Lesson 4- ", Raj Kamal, 14

15 Output characteristics of an n-channel JFET With a steady gate-source voltage of 1 V 2008 EDC Lesson 4- ", Raj Kamal, 15

16 2008 EDC Lesson 4- ", Raj Kamal, 16

17 V GS GS = 0 V V DS > 5 V assuming V p = 5 V 2008 EDC Lesson 4- ", Raj Kamal, 17

18 Case 3:. V GS 0 V and V DS = 10 V value at Junction Field Effect Transistor (JFET) 2008 EDC Lesson 4- ", Raj Kamal, 18

19 Output characteristics of an n-channel JFET With a steady gate-source voltage and V DS of 10 V When the drain-source voltage is increased to 10V the voltage across the channel walls at the drain end increases to 11V, but remains just 1V at the source end. The field across the walls near the drain end is now a lot larger than at the source end. As a result the channel near the drain is squeezed down greatly. (higher resistance to current flow) 2008 EDC Lesson 4- ", Raj Kamal, 19

20 Output characteristics of an n-channel JFET With a steady gate-source voltage of 10 V 2008 EDC Lesson 4- ", Raj Kamal, 20

21 Case 4:.. V GS = 1 V and V DS = 20 V value at Junction Field Effect Transistor (JFET) 2008 EDC Lesson 4- ", Raj Kamal, 21

22 Output characteristics of an n-channel JFET With a steady gate-source voltage of 20 V When the drain-source voltage is increased to 20V the voltage across the channel walls at the drain end increases to 21V, but remains just 1V at the source end. The field across the walls near the drain end is now a very larger than at the source end. As a result the channel near the drain is squeezed down greatly (chocked),. I DS = I DSS 2008 EDC Lesson 4- ", Raj Kamal, 22

23 Output characteristics of an n-channel JFET With a steady gate-source voltage of 20 V 2008 EDC Lesson 4- ", Raj Kamal, 23

24 Case 5: V GS = 2 V and V DS = 20 V value at Junction Field Effect Transistor (JFET) 2008 EDC Lesson 4- ", Raj Kamal, 24

25 Let us see what happen when negative voltage, says V GS = 2V, is applied to gate with respect to source (with V DS =0). The p + n junction are now reverse biased from the start, the channel is narrower, and channel resistance is now larger than in the V GS = 0 case EDC Lesson 4- ", Raj Kamal, 25

26 2008 EDC Lesson 4- ", Raj Kamal, 26

27 The drain current at reverse bias G and S flows when a small V DS applied is now smaller than in V GS = 0 case EDC Lesson 4- ", Raj Kamal, 27

28 When V DS = 3V, V GD across p + n junction at drain end is 5V, which is V P, so channel becomes pinch-off. Beyond pinch-off, I D is nearly saturated just as in the V GS = 0 case. Pinch-off occurs at V DS = V DS(sat), V DS(sat) = V P +V GS, where V GS is ve voltage (reducing V P ). For V DS >V DS(sat), I D becomes nearly saturated at value as I DS EDC Lesson 4- ", Raj Kamal, 28

29 Beyond pinch-of, with ve V GS, I DS is Where R AP (V GS ) is the effective resistance of the conducting n-channel from A to P, which depends on channel thickness and hence V GS. When V GS = -V P = -5V with V DS = 0, the two depletion layers touch over the entire channel length and the whole channel is closed EDC Lesson 4- ", Raj Kamal, 29 The channel said to be off.

30 Case 6:. V GS = 5 V and V DS = 20 V value at Junction Field Effect Transistor (JFET) 2008 EDC Lesson 4- ", Raj Kamal, 30

31 Depletion region (region depleted of free carriers (electrons and holes) 2008 EDC Lesson 4- ", Raj Kamal, 31

32 JFET Transfer Characteristics 2008 EDC Lesson 4- ", Raj Kamal, 32

33 Output Characteristics 2008 EDC Lesson 4- ", Raj Kamal, 33

34 I-V characteristics 2008 EDC Lesson 4- ", Raj Kamal, 34

35 I-V characteristics 2008 EDC Lesson 4- ", Raj Kamal, 35

36 Summary 2008 EDC Lesson 4- ", Raj Kamal, 36

37 We learnt JFET Characteristics Qualitative Discussion When VGS = 0, ID changes nearly linearly till pinch-off voltage and depletion region near the drain almost closes the channel 2008 EDC Lesson 4- ", Raj Kamal, 37

38 2008 EDC Lesson 4- ", Raj Kamal, 38

39 We learnt When VGS = 0, ID changes nearly linearly till pinch-off voltage. After pinch-off voltage the drai-source current remains constant at IDSS. When VGS is ve (for n-jfet) at certain value of VGS, ID does not increase and is EDC Lesson 4- ", Raj Kamal, 39

40 Depletion region (region depleted of free carriers (electrons and holes) 2008 EDC Lesson 4- ", Raj Kamal, 40

41 End of Lesson EDC Lesson 4- ", Raj Kamal, 41

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