# Lecture (03) The JFET

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1 Lecture (03) The JFET By: Dr. Ahmed ElShafee ١ JFET Basic Structure Figure shows the basic structure of an n channel JFET (junction field effect transistor). Wire leads are connected to each end of the n channel; the drain is at the upper end, and the source is at the lower end. Two p type regions are diffused in the n type material to form a channel, and both p type regions are connected to the gate lead. For simplicity, the gate lead is shown connected to only one of the p regions. A p channel JFET is shown in Figure ٢

2 Basic Operation To illustrate the operation of a JFET, Figure shows dc bias voltages applied to an n channel device. VDD provides a drain to source voltage and supplies current from drain to source. VGG sets the reverse bias voltage between the gate and the source, as shown. ٣ a negative gate voltage produces a depletion region along the pn junction, which extends into the n channel and thus increases its resistance by restricting the channel width. The channel width and thus the channel resistance can be controlled by varying the gate voltage, thereby controlling the amount of drain current, ID. ٤

3 The white areas represent the depletion region created by the reverse bias. It is wider toward the drain end of the channel because the reversebias voltage between the gate and the drain is greater than that between the gate and the source ٥ ٦

4 JFET Symbols The schematic symbols for both n channel and p channel JFETs are shown in Figure ٧ FET characteristic and perameters The JFET operates as a voltage controlled, constant current device. (VGS = 0 V), gate to the source both are grounded. As VDD (and thus VDS) is increased from 0 V, ID will increase proportionally, ٨

5 In this area, the channel resistance is essentially constant because the depletion region is not large enough to have significant effect This is called the ohmic region because VDS and ID are related by Ohm s law ٩ At point B, enters the active region where ID becomes essentially constant. As VDS increases from point B to point C, the reverse bias voltage from gate to drain (VGD) produces a depletion region large enough to offset the increase in VDS, thus keeping ID relatively constant. ١٠

6 Pinch Off Voltage For VGS =0 V, the value of VDS at which ID becomes essentially constant, point B on the is the pinch off voltage, VP. For a given JFET, VP has a fixed value. a continued increase in VDS above the pinchoff voltage produces an almost constant drain current. This value of drain current is IDSS (Drain to Source current with gate Shorted) and is always specified on JFET datasheets. ١١ IDSS is the maximum drain current that a specific JFET can produce regardless of the external circuit, and it is always specified for the condition, VGS 0 V. ١٢

7 Breakdown breakdown occurs at point C when ID increase very rapidly with any further increase in VDS. Breakdown can result in irreversible damage to the device, so JFETs are always operated below breakdown and within the active region (constant current) ١٣ ١٤

8 VGS Controls ID connect a bias voltage, VGG VGS is set to increasingly more negative values by adjusting VGG, a family of drain characteristic curves is produced. ID decreases as the magnitude of VGS is increased to larger negative values because of the narrowing of the channel ١٥ for each increase in VGS, the JFET reaches pinch off (where constant current begins) at values of VDS less than VP. ١٦

9 Cutoff Voltage The value of VGS that makes ID approximately zero is the cutoff voltage, VGS(off), ١٧ ١٨

10 for an n channel JFET, the more negative VGS is, the smaller ID becomes in the active region. When VGS has a sufficiently large negative value, ID is reduced to zero. This cutoff effect is caused by the widening of the depletion region to a point where it completely closes the channel ١٩ Comparison of Pinch Off Voltage and Cutoff Voltage The pinch off voltage VP is the value of VDS at which the drain current becomes constant and equal to IDSS and is always measured at VGS = 0 V. pinch off occurs for VDS values less than VP when VGS is nonzero. although VP is a constant, the minimum value of VDS at which ID becomes constant varies with VGS. G D S ٢٠

11 VGS(off) and VP are always equal in magnitude but opposite in sign. A datasheet usually will give either VGS(off) or VP, but not both. However, when you know one, you have the other. For example, if VGS(off) = 5 V, then VP = +5 V ٢١ Example 01 G D S ٢٢

12 Solution 1 G D S ٢٣ JFET Universal Transfer Characteristic range of VGS values from zero to VGS(off) controls the amount of drain current. For an n channel JFET, VGS(off) is negative, and for a p channel JFET, VGS(off) is positive. VGS does control ID, the relationship between them is very important. general transfer characteristic curve (transconductance curve) is relationship between VGS and ID ٢٤

13 ٢٥ drain characteristic curves, plotting values of ID for the values of VGS Each point on the transfer characteristic curve corresponds to specific values of VGS and ID on the drain curves. ٢٦

14 ٢٧ A JFET transfer characteristic curve is expressed approximately as ٢٨

15 Example 02 ٢٩ ٣٠

16 ٣١ ٣٢

17 JFET Forward Transconductance The forward transconductance (transfer conductance), gm, is the change in drain current ΔI D for a given change in gate tosource voltage ΔV GS. It is expressed as a ratio and has the unit of siemens (S). ٣٣ transfer characteristic curve for a JFET is nonlinear, gm is greater near the top of the curve (near VGS 0) than it is near the bottom (near VGS(off)) datasheet normally gives the value of gm measured at VGS = 0 V (gm0). Given gm0, you can calculate an approximate value for gm at any point on the transfer characteristic curve using the following formula: ٣٤

18 When a value of gm0 is not available, you can calculate it using values of IDSS and VGS(off ). ٣٥ Example 04 ٣٦

19 Solution 4 ٣٧ Input Resistance and Capacitance JFET operates with its gate source junction reverse biased, which makes the input resistance at the gate very high. high input resistance is one advantage of the JFET over the BJT. JFET datasheets often specify the input resistance by giving a value for the gate reverse current, IGSS, at a certain gate to source voltage. ٣٨

20 ٣٩ ٤٠

21 Example 05 ٤١ Answer 05 ٤٢

22 AC Drain to Source Resistance above pinch off, the drain current is relatively constant over a range of drain to source voltages. a large change in VDS produces only a very small change in ID. The ratio of these changes is the ac drain tosource resistance of the device, ٤٣ Thanks,.. See you next week (ISA), ٤٤

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