Field-Effect Transistor

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1 Philadelphia University Faculty of Engineering Communication and Electronics Engineering Field-Effect Transistor Introduction FETs (Field-Effect Transistors) are much like BJTs (Bipolar Junction Transistors). Similarities: Amplifiers Switching devices Impedance matching circuits ifferences: FETs are voltage controlled devices whereas BJTs are current controlled devices. FETs also have higher input impedance, but BJTs have higher gains. FETs are less sensitive to temperature variations and because of there construction they are more easily integrated on ICs. FETs are also generally more static sensitive than BJTs. In the BJT-the prefix bi-revealing that the conduction level is a function of two charge carriers, electrons and holes. The FET is unipolar device depending on either electrons or holes conduction. FET Types JFET Junction Field-Effect Transistor MOSFET Metal-Oxide Field-Effect Transistor -MOSFET epletion MOSFET E-MOSFET Enhancement MOSFET JFET JFET Construction There are two types of JFETs: n-channel (The n-channel is more widely used.) p-channel There are three terminals: rain () Source (S) are connected to the n-channel Lecturer: r. Omar aoud ١

2 Gate (G) is connected to the p-type material Basic Operation of a JFET JFET operation can be compared to a water spigot. The source of water pressure is the accumulation of electrons at the negative pole of the drain-source voltage. The drain of water is the electron deficiency (or holes) at the positive pole of the applied voltage. The control (gate) of flow of water is the gate voltage that controls the width of the n-channel and, therefore, the flow of charges from source to drain. JFET Operating Characteristics Three things happen when VGS = 0 and VS is increased from 0 to a more positive voltage The depletion region between p-gate and n- channel increases as electrons from n- channel combine with holes from p-gate. Increasing the depletion region, decreases the size of the n-channel which increases the resistance of the n-channel. Even though the n-channel resistance is increasing, the current (I ) from source to drain through the n-channel is increasing. This is because V S is increasing. If V GS = 0 and V S is further increased to a more positive voltage, then the depletion zone gets so large that it pinches off the n-channel. This suggests that the current in the n-channel (I ) would drop to 0A, but it does just the opposite as V S increases, so does I. Lecturer: r. Omar aoud ٢

3 At the pinch-off point: Any further increase in V GS does not produce any increase in I. V GS at pinchoff is denoted as Vp. I is at saturation or maximum. It is referred to as I SS. The ohmic value of the channel is maximum. As VGS becomes more negative, the depletion region increases. The JFET experiences pinch-off at a lower voltage (Vp). I decreases (I < ISS) even though VS is increased. Eventually I reaches 0A. VGS at this point is called Vp or VGS(off).. Also note that at high levels of V S the JFET reaches a breakdown situation. I increases uncontrollably if V S > V Smax. The region to the left of the pinch-off point is called the ohmic region. The JFET can be used as a variable resistor, where V GS controls the drain-source resistance (r d ). As V GS becomes more negative, the resistance (r d ) increases. ro rd 2 VGS 1 V P Where r o is the resistance with V GS =0 and r d the resistance at a particular level of V GS. Lecturer: r. Omar aoud ٣

4 The transfer characteristic of input-to-output is not as straightforward in a JFET as it is in a BJT. In a BJT, indicates the relationship between I B (input) and I C (output). In a JFET, the relationship of V GS (input) and I (output) is a little more complicated: Summary: I I V SS 1 V GS P 2 Lecturer: r. Omar aoud ٤

5 JFET Transfer (Characteristics) Curve This graph shows the value of I for a given value of V GS. Using I SS and Vp (V GS (off)) values found in a specification sheet, the transfer curve can be plotted according to these three steps: Step 1 V Solving for V GS = 0V, I I SS 1 V Step 2 Solving for V GS = V p (V GS(off) ) I = 0A Step 3 Solving for VGS = 0V to Vp GS P 2 I I SS Fig Transfer curve for Example 6.1. Fig Example 7.3. Lecturer: r. Omar aoud ٥

6 Exmple 6.1: MOSFET MOSFETs have characteristics similar to JFETs and additional characteristics that make then very useful. There are two types of MOSFETs: epletion-type Enhancement-Type The drain () and source (S) connect to the to n- doped regions. These n-doped regions are connected via an n-channel. This n-channel is connected to the gate (G) via a thin insulating layer of SiO2. The n-doped material lies on a p-doped substrate that may have an additional terminal connection called substrate (SS). A depletion-type MOSFET can operate in two modes: epletion mode Enhancement mode epletion Mode: The characteristics are similar to a JFET. When V GS = 0V, I = I SS When V GS < 0V, I < I SS Fig MOSFET. rain and transfer characteristics for an n-channel depletion-type Lecturer: r. Omar aoud ٦

7 The formula used to plot the transfer curve still applies: I I SS V 1 V GS P 2 Enhancement Mode: V GS > 0V Fig n-channel depletion-type MOSFET with VGS = 0 V and applied voltage V. I increases above I SS The formula used to plot the transfer curve still applies: I I SS V 1 V GS P 2 Enhancement-Type MOSFET Construction The drain () and source (S) connect to the n- doped regions. These n-doped regions are connected via an n-channel The gate (G) connects to the p-doped substrate via a thin insulating layer of SiO2 Lecturer: r. Omar aoud ٧

8 There is no channel The n-doped material lies on a p-doped substrate that may have an additional terminal connection called the substrate (SS) The enhancement-type MOSFET only operates in the enhancement mode. VGS is always positive As VGS increases, I increases As VGS is kept constant and VS is increased, then I saturates (ISS) and the saturation level, VSsat is reached Lecturer: r. Omar aoud ٨

9 Field-Effect Transistor Amplifiers Transconductance The relationship of V GS (input) to I (output) is called transconductance. Transconductance is denoted g m and given by: ΔI 2I g m ΔV GS V Where V GS =0V 2I SS g m0 V Where g m g m0 P V 1 V SS P P GS V 1 V GS P V I V GS GS 1 g m g m0 1 VP I SS V P g m0 I I SS The prefix trans- in the terminology applied to g m reveals that it establishes a relationship between an output and input quantity. The root word conductance was chosen because it is determined by a voltage-to-current ratio similar to the ratio that defines the conductance of a resistor. FET Impedance 1 Zo rd y os where: VS rd VGS constant I y os = admittance equivalent circuit parameter listed on FET specification sheets. FET AC Equivalent Circuit FET Biasing Lecturer: r. Omar aoud ٩

10 JFET Common-Source (CS) Fixed-Bias Configuration The input is on the gate and the output is on the drain. There is a 180 phase shift between input and output Zi R G Z R Z A A o o v v R V V o i V V o i r d r 10R d g g m m (r R d R ) r d 10R Lecturer: r. Omar aoud ١٠

11 Example 7.1: Lecturer: r. Omar aoud ١١

12 Solution: Lecturer: r. Omar aoud ١٢

13 Cont. Example 7.1: Solution: JFET Common-Source (CS) Self-Bias Configuration It eliminates the need for two dc supplies. The controlling V GS is now determined by the voltage across a resistor R s. Lecturer: r. Omar aoud ١٣

14 Bypassed R S : Unbypassed R S : Fig Self-bias JFET configuration including the effects of RS with rd = Ω. Lecturer: r. Omar aoud ١٤

15 Example 7.2: Lecturer: r. Omar aoud ١٥

16 Solution: Cont. Example 7.2.: Lecturer: r. Omar aoud ١٦

17 Solution: Common Source Voltage ivider Bias Configuration Lecturer: r. Omar aoud ١٧

18 Lecturer: r. Omar aoud ١٨

19 Example 7.5: Solution: Fig Example 7.5. Fig etermining the Q-point for the network of Fig Lecturer: r. Omar aoud ١٩

20 Example 7.6: Lecturer: r. Omar aoud ٢٠

21 Solution: ` Lecturer: r. Omar aoud ٢١

22 Source Follower (Common-rain) Configuration In a common-drain amplifier configuration, the input is on the gate, but the output is from the source. There is no phase shift between input and output. Zi R G Z r Z A A o o v v d R R S i S 1 g m 1 g m r d 10R S Vo g m (rd R S ) Vi 1 g m (rd R S ) Vo g mr S rd 10 V 1 g R m S Fig Network to be analyzed in Example 8.9. Lecturer: r. Omar aoud ٢٢

23 Lecturer: r. Omar aoud ٢٣

24 Example 8.9: Solution: Lecturer: r. Omar aoud ٢٤

25 Lecturer: r. Omar aoud ٢٥ JFET Common-Gate Configuration The input is on the source and the output is on the drain. There is no phase shift between input and output. d m d S i r g 1 R r R Z r d 10R m S i g 1 R Z d o r R Z 10 r o d R Z d d m i o v r R 1 r R R g V V A 10R r m v d R g A

26 Example 8.10: Solution: Lecturer: r. Omar aoud ٢٦

27 Fig Network for Example Lecturer: r. Omar aoud ٢٧

28 esign Example 1: Lecturer: r. Omar aoud ٢٨

29 esign Example 2: Lecturer: r. Omar aoud ٢٩

30 esign Example 3: Lecturer: r. Omar aoud ٣٠

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