UNIT I - TRANSISTOR BIAS STABILITY

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1 UNIT I - TRANSISTOR BIAS STABILITY OBJECTIVE On the completion of this unit the student will understand NEED OF BIASING CONCEPTS OF LOAD LINE Q-POINT AND ITS STABILIZATION AND COMPENSATION DIFFERENT TYPES OF BIASING CONSTANT CURRENT SOURCE THERMAL RUN AWAY BIASING CIRCUITS OF BJT, JFET, MOSFET BIASING Biasing in electronics is the method of establishing predetermined voltages and/or currents at various points of a circuit to set an appropriate operating point. The operating point of a device, also known as bias point or quiescent point (or simply Q-point), is the point on the output characteristics that shows the DC collector-emitter voltage (Vce) and the collector current (Ic) with no input signal applied. The term is normally used in connection with devices such as transistors. LOAD LINE A load line is used in graphic analysis of circuits; representing the constraint other parts of the circuit place on a non-linear device, like a diode or transistor. A load line represents the response of a linear circuit to which the nonlinear device in question is connected to. The operating point is where the parameters of the nonlinear device and the parameters of the linear circuit match according to how they are connected while still adhering to their internal systems. In the example on the right, the nonlinear diode is placed in series with a linear circuit consisting of a resistor and a voltage source. The load line represents the relationship between current and voltage in the linear part of the circuit while the exponential represents the relationship between current and voltage in the nonlinear device. Since the current going through three elements in series should be the same, the operating point of the circuit will be at the intersection of the exponential with the load line.

2 In a BJT circuit, the BJT has a different current-voltage(i C -V CE ) characteristic depending on the Base current. Placing a series of these curves on the graph shows how the base current will affect the operating point of the circuit. It should be noted that the load line is used for dc analysis, and has no bearing on smallsignal analysis once an operating point is identified. Q POINT The operating point of a device, also known as bias point or quiescent point (or simply Q-point), is the DC voltage and/or current which, when applied to a device, causes it to operate in a certain desired fashion. The term is normally used in connection with devices such as transistors and diodes which are used in amplification or rectification. FIXED BIAS (BASE BIAS) This form of biasing is also called base bias. In the example image on the right, the single power source (for example, a battery) is used for both collector and base of transistor, although separate batteries can also be used.

3 In the given circuit, V CC = I B R B + V be Therefore, I B = (V CC - V be )/R B For a given transistor, V be does not vary significantly during use. As V CC is of fixed value, on selection of R B, the base current I B is fixed. Therefore this type is called fixed bias type of circuit. Also for given circuit, V CC = I C R C + V ce Therefore, V ce = V CC - I C R C From this equation we can obtain V ce. Since I C = βi B, we can obtain I C as well. In this manner, operating point given as (V CE,I C ) can be set for given transistor. MERITS It is simple to shift the operating point anywhere in the active region by merely changing the base resistor (R B ). Very little number of components are required. DEMERITS The collector current does not remain constant with variation in temperature or power supply voltage. Therefore the operating point is unstable. Changes in V be will change I B and thus cause R E to change. This in turn will alter the gain of the stage. When the transistor is replaced with another one, considerable change in the value of β can be expected. Due to this change the operating point will shift.

4 COLLECTOR-TO-BASE BIAS This configuration employs negative feedback to prevent thermal runaway and stabilize the operating point. In this form of biasing, the base resistor R B is connected to the collector instead of connecting it to the DC source V CC. So any thermal runaway will induce a voltage drop across the R C resistor that will throttle the transistor's base current. By the Ebers Moll model, I c = βi b, and so From Ohm's law, the base current, and so Hence, the base current I b is If V be is held constant and temperature increases, then the collector current I c increases. However, a larger I c causes the voltage drop across resistor R c to increase, which in turn reduces the voltage across the base resistor R b. A lower base-resistor voltage drop reduces the base current I b, which results in less collector current I c. Because an increase in collector current with temperature is opposed, the operating point is kept stable. MERITS Circuit stabilizes the operating point against variations in temperature and β (ie. replacement of transistor) DEMERITS In this circuit, to keep I c independent of β, the following condition must be met.

5 VOLTAGE DIVIDER BIAS The voltage divider is formed using external resistors R 1 and R 2. The voltage across R 2 forward biases the emitter junction. By proper selection of resistors R 1 and R 2, the operating point of the transistor can be made independent of β. In this circuit, the voltage divider holds the base voltage fixed independent of base current provided the divider current is large compared to the base current. However, even with a fixed base voltage, collector current varies with temperature (for example) so an emitter resistor is added to stabilize the Q-point, similar to the above circuits with emitter resistor. MERITS Unlike above circuits, only one dc supply is necessary. Operating point is almost independent of β variation. Operating point stabilized against shift in temperature. DEMERITS In this circuit, to keep I C independent of β. FET BIASING Common FET Biasing Circuits JFET Depletion-Type MOSFET Fixed Bias Self-Bias Self-Bias Voltage-Divider Bias Voltage-Divider Bias

6 Enhancement-Type MOSFET Feedback Configuration For JFETS and Depletion-Type MOSFETs: Voltage-Divider Bias General Relationships For all FETs: For Enhancement-Type MOSFETs: JFETs JFETs differ from BJTs: Nonlinear relationship between input (V GS ) and output (I D ) FIXED-BIAS CONFIGURATION JFETs are voltage controlled devices, whereas BJTs are current controlled V S =0V V GS = -V GG V GS =V G - V S So: V G =V GS V DS =V D - V S So: V D =V DS Using KVL: V DS + I D R D - V DD. = 0 V DS = V DD - I D R D

7 See Example 6.1 Pg 293 V GSQ = -2V I DQ = 5.625mA V DS = V DD - I D R D = 4.75V. Find V GSQ, I DQ, V DS,V D, V G,V S. V GSQ, I DQ, V DS,V D, V G,V S. V DS =V D - V S So: V D =V DS =4.75V. V GS =V G - V S So: V G =V GS = - 2V V S =0V SELF-BIAS CONFIGURATION Self-Bias Calculations For the indicated loop: To solve this equation select an I D < I DSS and use the component value for R S. Plot this point: I D and V GS and draw a line from the origin of the axis to this point. Next plot the transfer curve using I DSS and V P (V P =

8 V GSoff in specification sheets) and a few points such the Q-point (I DQ ) to solve for the other voltages: as I D = I DSS /4 and I D = I DSS /2 etc. Where the first line intersects the transfer curve is the Q-point. Use the value of I D at Voltage-Divider Bias I G = 0A in FETs. Unlike BJTs, where I B affected I C; in FETs it is V GS that controls I D. Voltage-Divider Bias Calculations Using Kirchoff s Law: Rearranging and using I D =I S : Again the Q point needs to be established by plotting a line that intersects the transfer curve.

9 Voltage-Divider Q-point 1. Plot the line: By plotting two points: V GS = V G, I D =0 and V GS = 0, I D = V G /R S 2. Plot the transfer curve by plotting I DSS, V P and calculated values of I D. 3. Where the line intersects the transfer curve is the Q point for the circuit Voltage-Divider Bias Calculations Using the value of I D at the Q-point, solve for the other variables in the Voltage- Divider Bias circuit: Depletion-Type MOSFETs Depletion-type MOSFET bias circuits are similar to JFETs. The only difference is that the depletion-type MOSFETs can operate with positive values of V GS and with I D values that exceed I DSS.

10 Self-Bias 1. Plot line for V GS = V G, I D = 0 and I D = V G /R S, V GS = 0 These are the same calculations as used by a JFET circuit. 2. Plot the transfer curve by plotting I DSS, V P and Calculated values of I D. 3. Where the line intersects the transfer curve is the Q- point. Use the I D at the Q-point to solve for the other variables in the voltage-divider bias circuit. Voltage-Divider Bias 1. Plot line for V GS = V G, I D = 0 and I D = V G /R S, V GS = 0 2. Plot the transfer curve by plotting I DSS, V P and calculated values of I D. 3. Where the line intersects the transfer curve is the Q-point. Use the I D at the In the given circuit, V CC = I B R B + V be Therefore,

11 Voltage-Divider Bias Calculations Rearranging and using I D =I S : Again the Q point needs to be established by plotting a line that intersects the transfer curve. Using Kirchoff s Law: Voltage-Divider Q-point 2. Plot the transfer curve by plotting I DSS, V P and calculated values of I D. 3. Where the line intersects the transfer curve is the Q point for the circuit. 1. Plot the line: By plotting two points: V GS = V G, I D =0 and V GS = 0, I D = V G /R S

12 Voltage-Divider Bias Calculations Using the value of I D at the Q-point, solve for the other variables in the Voltage- Divider Bias circuit: Depletion-Type MOSFETs Depletion-type MOSFET bias circuits are similar to JFETs. The only difference is that the depletion-type MOSFETs can operate with positive values of V GS and with I D values that exceed I DSS. Self-Bias These are the same calculations as used by a JFET circuit. 1. Plot line for V GS = V G, I D = 0 and I D = V G /R S, V GS = 0 2. Plot the transfer curve by plotting I DSS, V P and calculated values of I D. 3. Where the line intersects the transfer curve is the Q- point. Use the I D at the Q-point to solve for the other variables in the voltage-divider bias circuit.

13 Voltage-Divider Bias 1. Plot line for V GS = V G, I D = 0 and I D = V G /R S, V GS = 0 2. Plot the transfer curve by plotting I DSS, V P and calculated values of I D. the line intersects the transfer curve is the Q- point. Use point to solve for the other variables in the voltage-divider bias circuit. These are the same calculations as used by a JFET circuit. Enhancement-Type MOSFET The transfer characteristic for the enhancement-type MOSFET is very different from that of a simple JFET or the depletion-type MOSFET. Feedback Biasing Arrangement I G =0A, V RG = 0V Therefore: V DS = V GS Which makes:

14 Feedback Biasing Q-Point 1. Plot the line using V GS = V DD, I D = 0 and I D = V DD / R D 4. Using the value of I D at the Q- point, solve for the other variables in the bias circuit. and V GS = 0 2. Plot the transfer curve using V GSTh, I D = 0 and V GS(on), I D(on) ; all given in the specification sheet. 3. Where the line and the transfer curve intersect is the Q- Point. Voltage-Divider Biasing Again plot the line and the transfer curve to find the Q-point. Using the following equations:

15 SUMMARY Biasing Connecting external DC power supply to the transistor. BJT Transistor operates in 3 regions namely cutoff, active, saturation region. BJT acts as an amplifier in active region. Load Line Line drawn on the output characteristics of a transistor under the DC operating condition. Q Point is a point on the load line which specifies the application of the transistor. Factors affecting the stability of transistor Change in temperature, Change in gain, variation of transistor parameter. Bias Stabilization is a process of stabilizing the Q point of the circuit. Stabilization Techniques 1. Fixed Bias o 2. Collector to base bias o 3. Self Bias o 4. Voltage divider bias Stability Factor It defines the variation of Ic with respect to gain, reverse saturation current, base emitter voltage. Ideal value of stability factor is zero. Bias Compensation Techniques 1. Compensation for change in Vbe 2. Compensation for change in ICo Thermal Runaway A heating process which damage the Transistor. FET Transistors operates in 3 regions namely cutoff, ohmic, saturation regions. JFET acts as amplifier in saturation region. Parameters of JFET - 1. Drain Resistance o 2. Amplification factor o 3. Transconductance Thermal Runaway does not occur in JFET due to positive temperature co-efficient of resistance. FET Transistors can act as Voltage Variable Resistors in ohmic region.

16 Review Questions 2 Mark 1. Briefly explain the concept of dc load line with the help of neat diagram. 2. What are the advantages and disadvantages of fixed bias circuit? 3. What is the bias compensation techniques using thermistor? 4. Define thermal resistance. 5. What is the need for biasing? 6. What is meant by compensation techniques? 7. What is the advantage of using emitter resistance in the context of biasing? 8. Draw the circuit that minimizes change in VBE due to temperature variation. 9. Define stability factor of an amplifier. What is its ideal Value? 10. Define pinch off voltage with respect to FET. 11. Define trans- conductance of JFET. 12. Why input impedance of JFET is high? 13. Compare BJT and FET. 14. Define dynamic resistance. 15. Draw the biasing arrangement of p channel JFET. 8 Mark 1. Draw the circuit diagram of self bias circuit using CE configuration and explain how it stabilizes operating point. 2. A self bias circuit has RE = 1 K, R1 = 130 K, R2 = 10 K. If Vcc and Rc are adjusted to give Ic = 1 ma at 10 C, calculate the variation in IC over temperature range of 10C, to 100 C. 3. Define 3 stability factors. Derive and explain the condition to thermal runaway. 4. What is meant by bias stability? What factors affect BJT biasing? 5. Draw the dc load line for any configuration. Obtain the quiescent point. 6. Derive an expression for stability factor. 7. Describe the stability in fixed bias and self bias and compare their performance. 8. Describe how dc and ac load lines are drawn. 9. Prove the self bias is better stable compared to collector to base bias. 10. Prove the collector to base is better than fixed bias.

17 11. Illustrate with necessary diagrams, the technique of biasing an enhancement MOSFET. 12. Explain briefly the technique of biasing a JFET for zero current drift with biasing. 13. Why is the self bias technique not used for enhancement MOSFET? 14. Explain voltage divider biasing for n-channel JFET. 15. Explain fixed bias circuit for n channel JFET.

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