Physics 481 Experiment 3

Transcription

1 Physics 481 Experiment 3 LAST Name (print) FIRST Name (print) TRANSISTORS (BJT & FET) npn BJT n-channel MOSFET 1

2 Experiment 3 Transistors: BJT & FET In this experiment transistor properties and transistor circuits will be explored. We will work bi-polar junction transistors (BJT) and field effect transistors (FET). Particularly, we will focus on the BJT current gain and voltage-current relationships for the FET drain and source electrodes with a constant gate to source voltage, along with a the relationship between the gate to source voltage versus the drain current. The laboratory will then explore the linear and saturation FET regimes in application to current source and the source follower. Part 1. BJT Transistors +15V BJT Current Gain Collector current A Set up the common emitter circuit shown in Figure 1 using 2N3904 transistor and other components as indicated in the figure. Use a DMM to measure the collector current I C. Use the DMM voltage measurement on the 4.7k resistor to calculate the base current I B. C IB +5V R Base current R 1 =4.7k Repeat the collector current and the base current measurements with variety of resistors, use Figure 1: Common Emitter Circuit 200k, 100k, 50k, 20k, and 10k I components. Plot the current gain ( β = ) as a function of base current. G R 2 =1k To check the temperature dependence of the current gain, start by putting back the 50k resistor. Now squeeze the transistor gently between your fingers and thumb. Record how the collector current changes with increasing temperature. Let the current come back to equilibrium, and check if you can observe the opposite effect by blowing vigorously on the transistor. Generalize your observations regarding temperature effects on transistor properties. 2

3 Emitter Follower Set up the emitter follower displayed in Figure 2. C=0.01uF V i R 1 =130k R =150k 2 2N3904 R 3 =7.5k +15V V o Inject sine and triangle signals from the Ground (or -15V) high output of your signal generator into Figure2: Emitter Follower Circuit the amplifier. Observe the input and output simultaneously on the oscilloscope. Describe what happens to your output as you turn the signal gain up to maximum. Explain the clipping phenomenon. At what voltages are the signals clipped? Check if you can observe small bumps at the bottom of the output for large inputs? Record your observations from oscilloscope and explain your results. Part 2. FET Transistors FET Characteristics: I D vs. V GS Set up the circuit shown in Figure 2 using 2N5485 transistor and other components as indicated in the figure. Use the DMM in ammeter mode to measure drain current I D. The DMM in voltmeter mode as shown in the figure will measure gate voltage V G. Explain the relationship between V G and gate-tosource voltage V GS for this circuit. Figure 3: FET Characteristics-I Use potentiometer (variable resistor) to regulate the gate voltage. At one extreme, use V GS =0, giving the maximum value for I D. (One should expect from the 2N5485 specification sheet that I DSS =I D (V GS =0) will fall in the range 4 10 ma.) Record the I DSS. Decrease V GS with potentiometer (making it more negative) and measure I D. After I D is reduced to zero, further decrease in V GS shall have no further effect. Determine threshold voltage V GS,off : record V GS for which the current just reaches zero on the 20 µa scale. (The specifications for the 2N5485 indicate the expected V GS,off values in the range of 0.5 to 4.0 V). Perform the measurements of voltage-current curve: beginning at V GS,off increase the current until it reaches approximately 0.3 µa and then record I D and V GS. Continue 3

4 increasing the current recording data (we suggest the approximate I D values of 0.3, 1, 3, 10, 30, 100, 300, 1000, and 3000 µa for the scan). Graph your data in ROOT and compare you results to the model, predicting the following dependence for the saturation regime: I D = I DSS ( 1 V GS V GS,off ) 2 In the plot use symbols for the experimental points and lines for the model predictions. Make a conclusion about how closely does the model fit your experimental data. Before breaking apart this test circuit, determine the V GS values where I D = 1.0, 0.5, and 0.1 ma to use in the next part of the lab. FET Current Source A simple current source can be made from a FET and a source resistor R S. The voltage drop across R S caused by the drain current I D causes the source voltage V S to rise above ground. Grounding V G, this makes V GS negative and acts to reduce I D. The connection between I D and V GS is a simple form of negative feedback: meaning that the action of the control (V GS ) in response to any change in the quantity (I D ), acts to return the quantity (I D ) to its equilibrium value. In other words, negative feedback causes the FET to hold I D constant. Use previously measured V GS for I D = 0.1,0.5,and 1.0mA to calculate the value of resistance R S (use V GS = I D R S relationship for each current, record all values and results in a table). Make a current source shown in Figure 4 using the same FET as in previous part. Use the standard resistor closest to your calculated values of R S. For each of your resistor values, measure the actual resistance. Place the resistor into the circuit as R S. Adjust the potentiometer to give the maximum current; V D should then be nearly 15 V. Here, the potentiometer is the load in the circuit. Increase its resistance and note what happens to I D and V D. Are the maximum I D and V D values achieved with a maximum or a minimum contribution of potentiometer resistance? Figure 4: FET Current Source For each resistor value make a table of the actual resistor value, the maximum current, and the V D when I D dropped to 90% of its maximum value. From your measurements of the I D and V D behavior, generalize your observations and describe what the FET is doing to control the current as you change the resistance of the load from one extreme to the other. 4

5 FET Characteristics: I D vs. V DS Set up the circuit shown in Figure 5. Start by adjusting the potentiometer so that V DS is nearly 15V. Measure I D and V DS. With the help of potentiometer decrease the voltage and record I D and V DS approximately every 2V until V DS is around 4V, and then take data every 1V. After I D has dropped ~1 ma below its maximum, begin recording data in approximately 1 ma steps. Make a graph and determine the ohmic and saturation ranges for this transistor. Figure 5: FET Characteristics-II 5