Today's Goals. Finish MOS transistor Finish NMOS logic Start CMOS logic

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1 Bi Today's Goals Finish MOS transistor Finish Start

2 Bi MOS Capacitor Equations Threshold voltage Gate capacitance V T = ms Q i C i Q II C i Q d C i 2 F n-channel - - p-channel ± ± Contributions to threshold voltage For enhancement type devices: for n-channel devices threshold voltage >0 p-channel devices threshold voltage < 0 C i = 0 ox t ox - - W L

3 Bi MOS Capacitor Characteristics You MUST know/understand MOS capacitor threshold voltage formula You MUST know/understand/be able to draw MOS capacitor band diagrams Refer to Streetman's book for details!!

4 Bi I G =0 MOS Transistor Operation I D =0 when V GS <V T I D staturates when V GD <V T Pinch-off is an educational tool to justify saturation. At the drain end the electrons are out-of equilibrium, so the equilibrium concentration formula does NOT apply. Pinch-off occurs due to velocity saturation at drain end of the channel.

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7 Bi MOS Transistor I-V characteristics Analytical derivation assumes Long channel Long channel implies uniform electric field within the channel Do you think measured values will match the analytical formula? Even for a physically long device? What can be done to predict the I-V curve of a transistor before fabrication? You are not responsible from the derivation of the transistor IV. You must be able to draw and understand the transistor band diagram.

8 Bi MOS Transistor I-V characteristics Operation Regimes: Off Linear Saturated Can you write equations for both NMOS and PMOS? Device transconductance parameter: K= W L ox t ox I G =0 Process transconductance parameter: k= ox t ox

9 Bi MOS Transistor I-V characteristics Operation Regimes: Off Linear Saturated Can you write equations for both NMOS and PMOS? Device transconductance parameter: K= W L ox t ox Process transconductance parameter: k= ox t ox

10 Bi MOS Transistor I-V characteristics NMOS V T 0 V GS V T OFF V GS V T V GS V T I DS 0 When linear V DS V GS V T LINEAR V DS V GS V T SAT 2 ] 2 I DS = K N [ V GS V T V DS V DS When SAT I DS = K N 2 V GS V T 2

11 Bi MOS Transistor I-V characteristics PMOS V T 0 V GS V T OFF V GS V T V GS V T I DS 0 When linear V DS V GS V T LINEAR V DS V GS V T SAT 2 ] 2 I DS = K P [ V GS V T V DS V DS When SAT I DS = K P 2 V GS V T 2

12 Bi MOS Transistor I-V characteristics NMOS/PMOS V GS V T OFF V GS V T V DS V GS V T LINEAR V GS V T V DS V GS V T SAT When linear I DS = K [ V GS V T V DS V 2 ] DS 2 When SAT I DS = K 2 V V GS T 2

13 Bi MOS Transistor I-V characteristics You MUST memorize NMOS/PMOS transistor I-V equations and characteristics

14 Bi MOS Secondary effects Body effect Subthreshold current Transit time Short channel effect Channel length modulation Velocity Saturation Gate leakage In fact, extremely important for MODERN MOS LOGIC. But complicates a first study of MOS LOGIC. These will be studied later, when we need them.

15 Bi NMOS Logic 3 types of pull-up devices Has static power dissipation Low-to-High delay is large Was used when there was no p-type MOS around

16 Bi Resistor load NMOS Logic VTC I LOAD =0 Identify the mode of the transistor and solve for I R =I DS(MN) OBSERVE: correct logic depends on the values of R and K

17 Bi Resistor load NMOS Logic VTC V I V T M NO I DMNO =0 V O =V DD OFF V i =V DD M NO LINEAR I D =K [ V DD V T V O V 2 ] O 2 I R = V DD V O R solve for V O from I D =I R Ignore the Vo^2 term to get V O = V DD R K V DD V T 1

18 Bi Resistor load NMOS Logic VTC Is M NO really in LINEAR region? K 1 ma V 2 Assume R 100 Ohm Assume V T =1V V O = =3.5V V DS = Yes device is linear BUT V O V T. If R=1000 Ohm V O 0.1V V T Correct logic operation depends on R and K

19 Bi Depletion load NMOS Logic VTC I LOAD =0 Identify the mode of the transistor and solve for -I DS(ML) =I DS(MN) OBSERVE: correct logic depends on the values of K L and K O

20 Bi P H =0 NMOS P L =V DD *I DDL Dynamic power dissipation important 2 P AC = f C L V DD

21 Bi NMOS Time to change output half-way Assume current stays equal to initial value after switching

22 Bi NMOS Fan-Out Fan out limited by tpmax emposed by system design

23 Bi design Design the pull-down network Select the Kp of pull-up transistor Pull-down network: Write down your logic function as f o =NOT(f pd ) The AND blocks in f pd will appear in series The OR block in f pd will appear in parallel Minimization of f pd for reduction in transistor count necessary