Electromagnetic Compatibility ( EMC )

Transcription

1 Electromagnetic Compatibility ( EMC ) Introduction about IC Immunity Testing

2 Agenda Semiconductor Immunity Test ESD ( ) Chip level test Human Body Mode MIL-STD 883E method or EIA/JESD 22-A114-A in EIA/JEDEC Machine Mode EIAJ-IC-121 method 20 or EIA/JESD 22-A115-A in EIA/JEDEC Charged-Device Mode EIA/JESD 22-A116-A in EIA/JEDEC System level test IEC Latch-up Physical Origin of Latch-up Latch-up Triggering Latch-up Prevention Latch-up Testing Voltage trigger Current trigger EIA/JEDEC No. 78

3 ESD Testing Concept Chip level ESD testing is just EOS issue IC level design to improve ESD System level ESD testing includes EOS and instant huge electrical magnetic field issue System level design will also effect ESD very much

4 Chip Level ESD Test ESD Mode Explain what is HBM MM CDM Compare the discharged current between these mode Test Method Kinds of the pin combination Testing process Failure decision

5 ESD Mode HBM Human Body Mode The oldest and most commonly used model 1.5K discharged resister to reduce the instant ESD current peak ESD Association HBM standard was recently revised The number of zaps per stress level and polarity has been reduced from 3 to 1. Also, the minimum time interval between zaps has been reduced from 1s to 300ms. The maximum rise time for an HBM wave form measured through a 500 ohm load was relaxed from 20 to 25ns

6 ESD Mode MM Machine Mode Originating in Japan as the result of trying to create a worst-case HBM event No discharged resister (like metal), so the instant ESD current peak is very serious

7 ESD Mode CDM Charged-Device Mode

8 ESD Mode CDM Charged-Device Mode

9 ESD Mode CDM Charged-Device Mode

10 Discharged Current

11 Test Level (Human-Body Model) (Machine Model) (Charged-Device Model) OK 2KV 200V 1KV Save 4KV 400V 1.5KV Super 10KV 1000V 2KV

12 Test Method The kinds of pin combination I/O

13 Test Method The kinds of pin combination I/O

14 Test Method The kinds of pin combination

15 Test Method The kinds of pin combination

16 Test Method Testing Process Stress number = 3 Zaps. (5 Zaps, the worst case). 1 zap/per sec. Stress step V ESD = 50V(100V) for V ZAP <=1000V V ESD = 100V(250V, 500V) for V ZAP > 1000V Starting V ZAP = 70% of averaged ESD failure threshold (V ESD )

17 Test Method Failure Decision IC ESD Input/Output 1 A( 10 A) 5.5V(VDDX1.1) 7V(VDDX1.4) I-V IC ESD Input/Output IC I-V 30% (20% 40%) IC ESD

18 Latch-up Overview Physical Origin of Latch-up Latch-up Triggering Latch-up Prevention Latch-up Testing

19 Latch-up Overview Happened just in CMOS technology N + + P_well or P + + N_well Via parasitic circuit effect npn + pnp BJT Resulting in shorting of the V DD and V SS Triggered by transient voltage or current but stop by current Positive feedback Chip will self-destruction or system failure

20 Latch-up Physical Origin of Latch-up CMOS Inverter Vdd Vss NMOS in out PMOS Vdd in G S D out G G B S D D S P+ N+ N+ P+ P+ pnp B N+ Rwell G D S Rsub npn N-Well P-Substrate Vss

21 Latch-up Physical Origin of Latch-up Rwell npn Parasitic Circuit Vdd Vbe1 Vbe2 Vss pnp Rsub G A P N P N J1 J2 J3 K G A K I VRB I IL IH VH VFB=Forward Breakdown voltage VRB=Reverse Breakdown voltage V H=Holding voltage IL=Latching current IH=Holding current VFB VAK

22 Latch-up Latch-up Triggering Latch-up Triggering lateral triggering a sufficient current is injected into the emitter of the lateral npn-transistor vertical triggering a sufficient current is injected into the emitter of the vertical pnp-transistor, and the current is multiplied by the common-base-current gain Current has to be injected either npn or pnp-emitter to initiate latchup, these conditions may occur at the I/O circuits employed on a CMOS chip

23 Latch-up Latch-up Prevention Latch-up Prevention Reducing the resistor values Reducing the gain of the parasitic transistor Two basic way Latch-up resistant CMOS process Layout techniques

24 Latch-up Latch-up Testing I trigger test

25 Latch-up Latch-up Testing positive I waveform

26 Latch-up Latch-up Testing -- negative I waveform

27 Latch-up Latch-up Testing -- V trigger test

28 Latch-up Latch-up Testing -- V Supply waveform

29 Latch-up Latch-up Testing timing spec. Symbol Time Interval Parameter Limits Min. Max. tr Trigger rise time 5us 5ms tf Trigger fall time 5us 5ms Twidth T3 T4 Trigger duration 2tr 1s TOS Trigger over-shoot ±5% of pulse voltage Tcool T4 T7 Cool down time Twidth Tmeasure T4 T5 Waiting time before measuring Isupply 3ms 5s