Technology Options for 22nm and Beyond
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- Katrina Fowler
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1 Technology Options for 22nm and Beyond Intel Fellow Intel Corporation Kelin J. Kuhn Director of Advanced Device Technology Kelin Kuhn / IWJT / Shanghai /
2 AGENDA Scaling Gate control Mobility Resistance Capacitance Summary Kelin Kuhn / IWJT / Shanghai /
3 AGENDA Scaling Gate control Mobility Resistance Capacitance Summary Kelin Kuhn / IWJT / Shanghai /
4 MOSFET Scaling Device or Circuit Parameter Scaling Factor Device dimension tox, L, W 1/κ Doping concentration Na κ Voltage V 1/κ Current I 1/κ Capacitance εa/t 1/κ Delay time/circuit VC/I 1/κ Power dissipation/circuit VI 1/κ 2 Power density VI/A 1 R. Dennard, IEEE JSSC, 1974 Classical MOSFET scaling was first described by Dennard in 1974 Kelin Kuhn / IWJT / Shanghai /
5 MOSFET Scaling Device or Circuit Parameter Scaling Factor Device dimension tox, L, W 1/κ Doping concentration Na κ Voltage V 1/κ Current I 1/κ Capacitance εa/t 1/κ Delay time/circuit VC/I 1/κ Power dissipation/circuit VI 1/κ 2 Power density VI/A 1 R. Dennard, IEEE JSSC, 1974 Classical MOSFET scaling ENDED at the 130nm node (and nobody noticed ) Kelin Kuhn / IWJT / Shanghai /
6 90 nm Strained Silicon Transistors NMOS PMOS High Stress Film SiGe SiGe SiN cap layer Tensile channel strain SiGe source-drain Compressive channel strain Strained silicon provided increased drive currents, making up for the loss of classical Dennard scaling Kelin Kuhn / IWJT / Shanghai /
7 45nm High-k + Metal Gate Transistors 45 nm HK+MG Hafnium-based dielectric Metal gate electrode High-k + metal gate transistors restored gate oxide scaling at the 45nm node Kelin Kuhn / IWJT / Shanghai /
8 THEN Scaling drove down cost Scaling drove performance Performance constrained Active power dominates Independent design-process Changes in Scaling 130nm 90nm 65nm 45nm 32nm Kelin Kuhn / IWJT / Shanghai /
9 Changes in Scaling THEN Scaling drove down cost Scaling drove performance Performance constrained Active power dominates Independent design-process NOW Scaling drives down cost Materials drive performance Power constrained Standby power dominates Collaborative design-process 130nm 90nm 65nm 45nm 32nm Kelin Kuhn / IWJT / Shanghai /
10 Consistent 2-year scaling 65nm WIDE m2 90nm TALL 1.0 m2 32nm WIDE m2 45nm WIDE m2 90 nm 65 nm 45 nm 32 nm 22 nm nm WIDE m2 projected Kelin Kuhn / IWJT / Shanghai /
11 Transistor Performance V, 100 na I OFF 32nm nm Drive Current (ma/um) nm 90nm 65nm 0.5 NMOS PMOS Gate Pitch (nm) nm transistors continue Moore s Law with improved drive at reduced pitch 11 Kelin Kuhn / IWJT / Shanghai /
12 Consistent SRAM Density Scaling Bitcell Area ( m 2 ) X bitcell area scaling 90nm 65nm 45nm 32nm Process generation 22nm K. Zhang, ISCC, 2009; M. Bohr IDF 2010 Kelin Kuhn / IWJT / Shanghai /
13 AGENDA Scaling Gate control Mobility Resistance Capacitance Summary Kelin Kuhn / IWJT / Shanghai /
14 MOSFET Challenges Resistance (Decreased S/D opening) Capacitance (Increased fringe to contact/facet) Contact Gate control (SCE limitations with smaller Leff) Spacer Gate Epi RSD Mobility (Reduced strain with decreased pitch) Kelin Kuhn / IWJT / Shanghai /
15 MOSFET Challenges Resistance (Decreased S/D opening) Capacitance (Increased fringe to contact/facet) Contact Gate control (SCE limitations with smaller Leff) Spacer Gate Epi RSD Mobility (Reduced strain with decreased pitch) Kelin Kuhn / IWJT / Shanghai /
16 Ultra-thin body with RSD Contact Spacer Gate Epi RSD Ultra-thin body (UTB) Kelin Kuhn / IWJT / Shanghai /
17 MuGFET Contact Spacer Gate Vertical thin body Kelin Kuhn / IWJT / Shanghai /
18 MuGFET VARIANTS FINFET TRIGATE PI-GATE Nearly ideal sub- gate threshold BOX slope Silicon (gates tied together) channel -GATE GAA (GATE-ALL-AROUND) Kelin Kuhn / IWJT / Shanghai /
19 Nanowire Contact Spacer Gate Nanowire Kelin Kuhn / IWJT / Shanghai /
20 Nanowire Contact Looking at all these in more detail Spacer Gate Nanowire Kelin Kuhn / IWJT / Shanghai /
21 Ultra-thin body with RSD Extension of planar technology (less disruptive to manufacturing) Benefits Improved RDF (low doped channel) Compatible with RSD technology Excellent channel control Potential for body bias Kelin Kuhn / IWJT / Shanghai /
22 Ultra-thin body with RSD Capacitance (Increased fringe to contact/facet) Rext: (Xj/Tsi limitations) Challenges Variation: (film thickness changes affects VT and DIBL) Strain: (strain transfer from S/D into the channel) Manufacturing: (requires both thin Tsi and thin BOX) Performance: (transport challenges with thin Tsi) Kelin Kuhn / IWJT / Shanghai /
23 Barral CEA-LETI IEDM 2007 Ultra-thin body Cheng IBM VLSI 2009 Lg=25nm Tsi=6nm Kelin Kuhn / IWJT / Shanghai /
24 MuGFET Benefits Double-gate relaxes Tsi requirements Fin Wsi > UTB Tsi (less scattering, improved VT shift) Nearly ideal subthreshold slope (gates tied together) Improved RDF (low doped channel) Can be on bulk or SOI Excellent channel control Kelin Kuhn / IWJT / Shanghai /
25 MuGFET with RSD Double-gate relaxes Tsi requirements Fin Wsi > UTB Tsi (less scattering, improved VT shift) Nearly ideal subthreshold slope (gates tied together) Benefits Improved RDF (low doped channel) Compatible with RSD technology Excellent channel control Kelin Kuhn / IWJT / Shanghai /
26 MuGFET Benefits Double-gate relaxes Tsi requirements Fin Wsi > UTB Tsi (less scattering, improved VT shift) Possibility for independent gate operation Improved RDF (low doped channel) Excellent channel control Kelin Kuhn / IWJT / Shanghai /
27 MuGFET Capacitance (fringe to contact/facet) Plus, additional dead space elements Variation (Mitigating RDF but acquiring Hsi/Wsi/epi) Challenges Gate wraparound (Endcap coverage) Small fin pitch (2 generation scale?) Fin/gate fidelity on 3 D (Patterning/etch) Fin Strain engr. (Effective strain transfer from a fin into the channel) Rext: (Xj/Wsi limitations) Topology (Polish / etch challenges) Kelin Kuhn / IWJT / Shanghai /
28 Hisamoto Hitachi / Berkeley IEDM 1998 [3] Kelin Kuhn / IWJT / Shanghai /
29 Kavalieros Intel IEDM 2006 MuGFET Vellianitis NXP-TSMC IEDM 2007 Kelin Kuhn / IWJT / Shanghai /
30 Kang Sematech VLSI 2008 MuGFET Chang TSMC IEDM 2009 Kelin Kuhn / IWJT / Shanghai /
31 Nanowire Benefits Nearly ideal subthreshold slope (gates tied together) Nanowire further relaxes Tsi / Wsi requirements Improved RDF (low doped channel) Excellent channel control Kelin Kuhn / IWJT / Shanghai /
32 Nanowire Benefits Nearly ideal subthreshold slope (gates tied together) Nanowire further relaxes Tsi / Wsi requirements Improved RDF (low doped channel) Compatible with RSD technology Excellent channel control Kelin Kuhn / IWJT / Shanghai /
33 Nanowire Integrated wire fabrication (Epitaxy? Other?) Mobility degradation (scattering) Gate conformality (dielectric and metal) Wire stability (bending/warping) Challenges Capacitance (fringe to contact/facet) Plus, additional dead space elements Variation (Mitigating RDF but acquiring a myriad of new sources) Fin Strain engr. (Effective strain transfer from wire into the channel) Rext: (Xj/Wsi limitations) Topology (Polish / etch Fin/gate fidelity on 3 D (Patterning/etch) Kelin Kuhn / IWJT / Shanghai challenges) /
34 Yeo Samsung IEDM 2006 Nanowire FETs Dupre CEA-LETI IEDM 2008 Kelin Kuhn / IWJT / Shanghai /
35 Wong NUS Singapore VLSI 2009 Nanowire FETs Bangsaruntip IBM IEDM 2009 Kelin Kuhn / IWJT / Shanghai /
36 MOSFET Challenges Resistance (Decreased S/D opening) Capacitance (Increased fringe to contact/facet) Gate control (SCE limitations with smaller Leff) Mobility (Reduced strain with decreased pitch) Kelin Kuhn / IWJT / Shanghai /
37 Transistor Performance Trend Drive Current (ma/um) V, 100 na I OFF 90nm 130nm 65nm 45nm 32nm Strain Hi-k-MG Other Classic scaling PMOS Gate Pitch (nm) 100 Strain is a critical ingredient in modern transistor scaling Strain was first introduced at 90nm, and its contribution has increased in each subsequent generation Kelin Kuhn / IWJT / Shanghai /
38 Etch-stop nitride (CESL) 28-35% 7% Ito NEC IEDM 2000 NMOS SiN strain Pidin Fujitsu IEDM 2004 N and PMOS Mayuzumi Sony IEDM 2007 Dual-cut stress liners (MG process) Kelin Kuhn / IWJT / Shanghai /
39 Strain: Pitch dependence Idsat % gain Normalized Idsat Pitch (nm) Pitch (nm) 100 NMOS Pitch degradation increases with film pinchoff, requires higher stress, thinner films PMOS esige S/D mobility strongly dependent on pitch Auth, Intel, VLSI 2008 Kelin Kuhn / IWJT / Shanghai /
40 Embedded SiGe (PMOS) Thompson Intel IEDM 2002 / 2004 Ghani Intel IEDM 2003 Chidambaram TI / Applied Materials VLSI Kelin Kuhn / IWJT / Shanghai /
41 Embedded Si:C (NMOS) ~9% from SiC Ang NUS-Singapore IEDM 2004 Selective epi SiC (undoped) Yang IBM IEDM 2008 In-situ epi P-SiC Chung Nat l Chiao Tung U. VLSI 2009 Implanted C + SPE Kelin Kuhn / IWJT / Shanghai /
42 Strain: Pitch dependence Idsat % gain Normalized Idsat Pitch (nm) Pitch (nm) 100 NMOS Pitch degradation increases with film pinchoff, requires higher stress, thinner films PMOS esige S/D mobility strongly dependent on pitch Auth, Intel, VLSI 2008 Kelin Kuhn / IWJT / Shanghai /
43 Strain: Pitch dependence Idsat % gain less sensitive 1.4 to pitch? 1.3 Normalized Idsat Pitch (nm) Pitch (nm) 100 What about strain options NMOS Pitch degradation increases with film pinchoff, requires higher stress, thinner films PMOS esige S/D mobility strongly dependent on pitch C. Auth, VLSI 2008 Kelin Kuhn / IWJT / Shanghai /
44 Stress Memorization (SMT) 11-15% >27% Ota Mitsubishi IEDM 2002 NMOS SMT Chen TSMC VLSI 2004 NMOS SMT Wei AMD VLSI 2007 Multiple liners Kelin Kuhn / IWJT / Shanghai /
45 Metal stress (gate and contact) Different gate stack Raised S/D NMOS PMOS % 1000 VDD = 1.0V 1000 VDD = 1.0V Ioff (na/ m) % 10 Compressive Gate Control Idsat(mA/ m) Ioff (na/ m) % Tensile Contact Control Idsat(mA/ m) Kang Sematech IEDM 2006 Auth Intel VLSI 2008 Kelin Kuhn / IWJT / Shanghai /
46 Enhanced PMOS strain: Gate last HiK-MG Before gate removal After gate removal 14% RMG Wang Sony VLSI 2007 Auth Intel VLSI 2008 Kelin Kuhn / IWJT / Shanghai /
47 (100) surface top down ORIENTATION (110) surface top down <110> <100> (100) <110> <110> Standard wafer / direction (100) Surface / <110> channel (100) Surface / <100> (a 45 degree wafer) Both <110> directions are the same. (110) <100> <111> <110> Non-standard (110) Surface Three possible channel directions <110> <111> and <100> <100> Kelin Kuhn / IWJT / Shanghai /
48 (100) surface top down (110) surface top down (100) <110> <110> <100> <110> Standard wafer / direction (100) Surface / <110> channel (100) Surface / <100> (a 45 degree wafer) Both <110> directions are the same. (110) <100> <111> <110> Non-standard (110) Surface Three possible channel directions <110> <111> and <100> <100> (100) BEST NMOS (110) <110> BEST PMOS Yang AMD/IBM EDST 2007 Kelin Kuhn / IWJT / Shanghai /
49 PMOS Vertical Devices on (100) Put NMOS at 45degrees to PMOS? Chang - IBM TED 2004 [54] <110> channel (110) Surface Kinugawa-Toshiba VLSI 1986 (110) surface <110> channel results when a VFET is fabricated on typical (100) Si - good for PMOS, not for NMOS Kelin Kuhn / IWJT / Shanghai /
50 Put NMOS at 45degrees to Put PMOS? NMOS at 45degrees to PMOS? NMOS Vertical Devices on (100) <100> channel (100) Surface (100) surface <100> channel for a VFET fabricated at 45 degrees typical (100) Si very challenging for lithography at 22nm node Chang - Berkeley Proc. IEEE 2003 [56] Kelin Kuhn / IWJT / Shanghai /
51 Strain and Orientation Piezoresistive coefficient as a function of direction Udo Infineon Proc. IEEE Sensors 2004 NMOS PMOS Kelin Kuhn / IWJT / Shanghai /
52 Krishnamohan Stanford IEDM 2008 Kelin Kuhn / IWJT / Shanghai /
53 MOSFET Challenges Resistance (Decreased S/D opening) Capacitance (Increased fringe to contact/facet) Gate control (SCE limitations with smaller Leff) Mobility (Reduced strain with decreased pitch) Kelin Kuhn / IWJT / Shanghai /
54 Planar Resistive Elements R CONTACT R SILICIDE R INTERFACE R EPI R ACCUMULATION R SPREADING Kelin Kuhn / IWJT / Shanghai /
55 Technology trends Xj/Tsi, Lg, Racc XJ / Tsi (nm), Lgate (nm) XJ Lg Rratio Tsi % 30% 20% 10% 0% IDEAL Racc/(Vdd/Idsat) Rchannel Racc RESISTANCE ( / m) TECHNOLOGY YEAR ITRS 2007 [19] TECHNOLOGY NODE Noori - Applied Materials TED 2008 [20] 40 Kelin Kuhn / IWJT / Shanghai /
56 RTA effective annealing times Cycle Rampup Rate (C/s) Typical peak time (s) Rampdown Rate (C/s) Effective Time (s) Soak ~5+t hold Spike 250 < ~1 Flash 1e5-1e6 <1e-6 ~1e ms Scanning laser 1e5-1e6 <1e-6 >1e ms Melt (laser) 1e7-1e8 <1e-8 >1e ns Effective annealing times are computed with realistic ramp shapes, assuming dominant Ea~5eV. Kelin Kuhn / IWJT / Shanghai /
57 Annealing techniques: by physics of activation Melt Laser Flash or SubMelt Laser Temp (C) Spike RTA Soak RTA Int diff dop subs Int clus LPER 311 form SPER B diff As diff 311 diss BIC diss E-10 1.E-08 1.E-06 1.E-04 1.E-02 1.E+00 1.E+02 1.E+04 1.E+06 Characteristic Time (s) Kelin Kuhn / IWJT / Shanghai /
58 Temp (C) Annealing techniques: by physics of activation Melt Laser Flash/submelt laser processes have the potential to freeze dopant profiles in place Flash or SubMelt Laser Spike RTA Soak RTA Int diff dop subs Int clus LPER 311 form SPER B diff As diff 311 diss BIC diss E-10 1.E-08 1.E-06 1.E-04 1.E-02 1.E+00 1.E+02 1.E+04 1.E+06 Characteristic Time (s) Kelin Kuhn / IWJT / Shanghai /
59 Submelt Laser Anneal Test Stand laser melt monitor focusing optic velocity feedback encoder spindle and wafer chuck attenuator power monitor shutter focusing optics retractable alignment microscope scanning stage Guassian beam: 400 m wide (FWHM) Spinning stage: dwell time s Constant dwell time and track spacing are maintained by synchronizing spin speed and x-stage position Kelin Kuhn / IWJT / Shanghai /
60 Submelt Laser Anneal Test Results Concentration (atoms/cm3) 1E+22 1E+21 1E+20 1E+19 1E+18 1E+17 Junction depth = 26 nm Sheet resistance = 150 /sq Phosphorus Depth (nm) #0 - No Laser #4-91%, 60us #5-88%, 60us #6-85%, 60us #7-54%, 200us Concentration (atoms/cm3) 1.00E E E E E E+17 Junction depth = 28 nm, Sheet resistance = 150 /sq Arsenic #0 Laser Power = 0 #0 Laser Power = 0 #9 Laser Power = 50% #7 Laser #7 Laser Power = = 54% #9 Laser Power = 50% 1.00E (nm) Depth (nm) Freezing implants in place: Submelt laser anneal showing no diffusion after 200 μs anneal Kelin Kuhn / IWJT / Shanghai /
61 Dopant solubility limits are controlled by slower rather than faster processes permitting super-activation 1500 Temp (C) Annealing techniques: by physics of activation Melt Laser Slow characteristic times include clustering or precipitation reactions Flash or SubMelt Laser Spike RTA Soak RTA Int diff dop subs Int clus LPER 311 form SPER B diff As diff 311 diss BIC diss 600 SPER 500 Fast characteristic times include Si Int diffusion and clustering and dopant substitutionality Characteristic via Time (s) substitutional-interstitial exchange reaction 1.E-10 1.E-08 1.E-06 1.E-04 1.E-02 1.E+00 1.E+02 1.E+04 1.E+06 Kelin Kuhn / IWJT / Shanghai /
62 Superactivation with solid-phase epitaxial regrowth (SPER) Concentration (cm-3) Concentration (cm-3) 1E+22 1E+21 1E+20 1E+19 1E+18 1E+17 1E+21 1E+20 1E+19 1E+18 1E+17 Laser Anneal 1E16, Rs=73 4E15, Rs=91 2E15, Rs=132 1E15, Rs=205 B in Si Depth (nm) B in Si Depth (nm) 1E+22 1E+21 1E+20 1E+19 1E+18 1E+17 1E+21 1E+20 1E+19 1E+18 1E+17 B in Si Depth (nm) B in Si 4E14 RTA 1E15, 2E15, 4E C 980 C 1000 C 1020 C Depth (nm) Temperature Dose Laser melt anneal vs RTA, showing increased abruptness and non-equilibrium enhanced activation (superactivation). Kelin Kuhn / IWJT / Shanghai /
63 MOSFET Challenges Resistance (Decreased S/D opening) Capacitance (Increased fringe to contact/facet) Gate control (SCE limitations with smaller Leff) Mobility (Reduced strain with decreased pitch) Kelin Kuhn / IWJT / Shanghai /
64 Planar Capacitive Elements Cfringe to Contact Cfringe to facet Cjunction Cfringe to diffusion (of/if) Cxud - device component of Cov (XUD-based) Gated-edge junction Cchannel component of Cgate Area junction Kelin Kuhn / IWJT / Shanghai / Kuhn, Intel, IEDM SC 2008
65 Innovative Spacer Technologies SPACER REMOVAL Liow NUS Singapore EDL 2008 SiBCN (Low-K) SPACER Ko TSMC VLSI 2008 Kelin Kuhn / IWJT / Shanghai /
66 AGENDA Scaling Gate control Mobility Resistance Capacitance Summary Kelin Kuhn / IWJT / Shanghai /
67 Looking Forward Low risk Enhancements in strain technology Enhancements in annealing/implant technology Medium Risk Optimized substrate and channel orientation Reduction in MOS parasitic resistance Reduction in MOS parasitic capacitance High risk UTB devices MuGFETS Nanowires Kelin Kuhn / IWJT / Shanghai /
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