Final Exam Topics. IC Technology Advancement. Microelectronics Technology in the 21 st Century. Intel s 90 nm CMOS Technology. 14 nm CMOS Transistors

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1 ANNOUNCEMENTS Final Exam: When: Wednesday 12/10 12:30-3:30PM Where: 10 Evans (last names beginning A-R) 60 Evans (last names beginning S-Z) Comprehensive coverage of course material Closed book; 3 sheets of notes & calculator allowed For Chunlong s students (Lab Sections 17 & 20): Section 17 (Wed 3-6 PM) students should attend an alternate section, to have their Tutebots checked off before Thu. 8 PM Students in Lab Sections 17 & 20 (Wed 3-6 PM & Thu 5-8 PM) can receive their deposit checks back next week. Prof. King s Office Hours tomorrow: 1-5 PM, 476 Cory Final Exam Topics 1. Circuit analysis 2. Equivalent circuits 3. Op-amp circuits 4. First-order circuits / transient response 5. Semiconductor properties, pn diodes 6. MOSFET devices and circuits 7. Logic circuits (including delay analysis) 8. CMOS process & layout Microelectronics Technology in the 21 st Century Reference Reading Rabaey et al.: Section IC Technology Advancement The growth of the semiconductor industry has been tied to transistor scaling Investment Technology Scaling Better Performance/Cost Market rowth $141B in 2002 ATE LENTH (nm) 10 ITRS 2001 Projection LOW POWER HIH PERFORMANCE YEAR Intel s 90 nm CMOS Technology Used for volume manufacturing of ICs on 300 mm wafers beginning 4Q03 14 nm CMOS Transistors Hokazono et al., Toshiba Corporation, presented at the International Electron evices Meeting (San Francisco, CA) ec nm SiO x N y gate dielectric Poly-Si 0.9 e 0.1 gate L g = 50 nm T ox = 1.2 nm Strained Si channel

2 Bulk-Si MOSFET Scaling Leakage current is the main challenge to scaling To suppress leakage, we need to employ: Higher body doping lower carrier mobility, higher junction capacitance, increased junction leakage Thinner gate dielectric higher gate leakage Ultra-shallow S/ junctions higher R series Metal-Oxide-Semiconductor Field-Effect Transistor: esired characteristics: High ON current (I dsat ) Low OFF current Substrate L eff L g X j N sub T ox Advanced MOSFET Structures Thin-Body MOSFETs Must control leakage in order to scale down L g Most of the leakage occurs far from the SiO 2 interface Let s get rid of it! Ultra-Thin Body ouble SOI T Si 1 V g Thin-Body Bulk MOSFET Buried Oxide Substrate SOI Wafer SiO 2 Silicon Substrate T BOX T ox SOI 2 Common feature: A thin body, such that no conduction path is far from the gate T Si Ultra-Thin-Body MOSFET UTB suppresses leakage Thick S/ => low R series M. Takamiya et al., Proc ISRS, p. 215 B. Yu et al., Proc ISRS, p. 623 Current [A/um] 1.E-06 1.E-08 1.E-10 1.E-12 L g = 12 nm T ox = 2 nm Simulated I d -V g 1.E-02 V ds =1V 1.E-04 Subthreshold swing S (units: mv/dec) T si =8nm T si =6nm T si =4nm Voltage [V] Current, Id [ma/mm] Measured UTB MOSFET I d -V d PMOS L g = 30nm T si = 5nm T ox =2.1nm NMOS V g -V t =1.0V L g = 80nm T si = 20nm 0.85V T ox =2.3nm V 0.7V 400 g -V t =-1.1V V V V V 0.4V V 0.25V 0-0.1V Voltage, V d [V] ood I dsat achieved with thick S/ structure Y.-K. Choi et al., IEM 1999

3 UTB MOSFET Scaling Issues for bulk-si MOSFET scaling obviated Body does not need to be heavily doped T ox does not need to be scaled as aggressively Ultra-shallow S/ junction formation is not an issue Body thickness must be less than ~1/3 x L g Formation of uniformly thin body is primary challenge For T Si < 4 nm, quantum confinement & interface roughness V T variation and degraded g m K. Uchida et al., IEM 2002 Current Flow ouble- FinFET Self-aligned gates straddle thin silicon fin Current flows parallel to wafer surface Length = L g 1 2 Fin Height = H fin = W Fin Width W fin = T Si FinFET Layout Scaling L g to 10 nm Layout is similar to that of conventional MOSFET 15nm FinFET fabricated at UC Berkeley ATE 10 nm 20 nm SOURCE RAIN technology transferred Poly-Si Si fin NiSi 220Å SiO 2 cap L g =10nm Bulk-Si MOSFET FinFET Y.-K. Choi et al., presented at the 2001 Int l Electron evices Meeting SiO 2 B. Yu et al., presented at the 2002 Int l Electron evices Meeting CMOS FinFETs fabricated using standard tools at AM (optical lithography plus photoresist trimming) 10 nm L g FinFET I d -V d Circuit Performance Comparison No channel doping is needed in thin-body FETs higher I dsat achieved, dopant fluctuation effects avoided FO4 Inverter elay [ps] Mixed mode circuit simulations using MEICI version 4.1 L gate =35nm Poly Mid-gap Metal Bulk S-UTB L. Chang et al., Proc. IEEE 91 (2003) B. Yu et al., IEM Technical igest, pp , 2002 V T must be adjusted by gate work function engineering

4 N + T body Molybdenum-d FinFETs Poly-Si Mo W S Y.-K. Choi et al., 2002 IEM N + L gate Voltage, V g [V] Tilted N implantation (60 ) used for sidewall gates N implantation lowers gate work function Current, Id [A/um] L g =80nm, T Si =10nm V ds =0.05V V T shift Mo MoN(N 2 =5x10 15 cm -2 ) MOSFET Scaling to the Limit high-k dielectric (?) L g (nm): S Si classical ultra-thin body double-gate metal gate low channel doping S SOI SiO 2 Si substrate S SOI IC Technology Challenges Limits to transistor scaling exist Power is an issue of increasing importance Portable & wireless-communication products require high speed, low cost & very low power Alternative approaches are needed innovative circuit & system designs novel semiconductor devices that enable more efficient circuit designs heterogeneous integration Heterogeneous Integration Enhanced functionality/value of IC products Example: Integrated Micro-ElectroMechanical evices low-power, wireless building blocks MEMS antennas, microswitches, filters cooler microprocessors micropumps, valves, and channels for cooling smart sensors environmental monitoring improved energy efficiency, emergency response, contamination detection bio chips microfluidics biochemical sensors, NA analysis chips, drug delivery MEMS Technology Surface Micromachining (cross-sectional view) structural film sacrificial layer Si wafer substrate Mechanical structures can be made using conventional microfabrication techniques Structures are freed by selective removal of sacrificial layer(s) Polycrystalline silicon is the preferred structural material as strong as steel resists fatigue -- requires high annealing temperatures ( 900 o C)

5 Surface Micromachined Resonator Benefit of Multiple Structural Layers Example: Hinged Structure Electrostatic force is applied by a comb drive electrode to a suspended shuttle. Motion is detected capacitively by a sense comb electrode. Top view of masks out-of-plane movement Cross-sectional views Micromachines Examples of MEMS Products Chemical and pressure sensors Inertial sensors accelerometers and gyroscopes Optical modulators micro-mirrors for communications, projection displays M TM Projection isplay Chip Texas Instruments Inc. Mirrors are made using metal layers (Al, alloys) - sacrificial material is photoresist SEM image of pixel array Schematic of 2 pixels Each mirror corresponds to a single pixel, programmed by an underlying memory cell to deflect light either into a projection lens or a light absorber. Integrated MEMS Technology For low cost & high performance, we want: Low thermal process budget can use semiconductor foundry for electronics, then add MEMS in a modular fashion Capabilities similar to poly-si MEMS can leverage MEMS foundry CMOS foundry processes, and MEMS industry design experience foundry MEMS Si Substrate

6 Enter Silicon-ermanium Sie can be processed at significantly lower process temperatures than Si ( 450 o C) III IV V - Conventional process tools are used for deposition and patterning B C N Al Si P a e As Properties are similar to those of Si, and can be tailored by adjusting e content The IC industry has significant experience with Sie Sie imems emonstration High-performance MEMS can be fabricated directly on top of conventional CMOS circuits, using silicon-germanium for the structural layers Resonator next to Amplifier conventional layout of integrated MEMS resonator amplifier Resonator on top of Amplifier smaller area --> lower cost reduced interconnect parasitics --> improved performance A. E. Franke et al., Solid-State Sensor and Actuator Workshop Technical igest, pp , June 2000 Sie imems Resonator Response S. A. Bhave et al., Solid-State Sensor and Actuator Workshop Technical igest, pp , 2002 T/R (db) 19.6kHz comb-drive: Q ~ 31, Future Application: RF MEMS Poly-Sie RF MEMS technology Shielded Interconnect to rive Electrode C Bias to Resonator 5-level metal foundry CMOS rive Electrode Microshell Encapsulation (anchors not shown) BLR Sense Electrode T max < 425 o C Shielded Vertical Signal Path to of Input Transistor Frequency (Hz) Advantages of MEMS filters: small size, low cost low phase noise, high Q(?) Conclusion Transistor scaling can extend to below 10 nm advanced structures, materials & processes needed Investment evice & esign Innovation, Heterogeneous Integration Market rowth Lower Cost and/or Lower Power ATE LENTH (nm) YEAR LOW POWER HIH PERF. Alternative approaches to scaling will provide improvements in cost, power and/or performance, to sustain the silicon revolution well beyond 30 yrs

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