32nm Technology and Beyond
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1 32nm Technology and Beyond Paolo Gargini Chairman ITRS IEEE Fellow Director of Technology Strategy Intel Fellow ISS Europe 2009 P. Gargini 1
2 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology highlights Beyond 32nm Conclusions ISS Europe 2009 P. Gargini 2
3 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology highlights Beyond 32nm Conclusions ISS Europe 2009 P. Gargini 3
4 The Ideal MOS Transistor Metal Source Drain Gate Insulator Fully Surrounding Metal Electrode Fully Enclosed, Depleted Semiconductor High-K Gate Insulator Band Engineered Semiconductor Low Resistance Source/Drain From My Files ISS Europe 2009 P. Gargini 4
5 Staged Investment Aligned to Risks Step 5 Step 4 Step 3 Step 2 Step 1 External Research $/Year ~ 10 7 Research Pathfinding Development Manufacturing ~ 10 8 ~ 10 9 ~ Risk & Options High Moderate Low Create very Evaluate Focus on Synchronize Copy exactly, early on options, choices, and ramp rapidly options collaborate reduce risk integrate externally externally ISS Europe 2009 P. Gargini 5
6 The New Scaling Paradigm Classical Scaling L G T ox V DD L G T ox V DD Strain High-K Metal-G Tri-Gate New New ISS Europe 2009 P. Gargini 6
7 Strained P-Channel Transistor Mobility Innovation Strained N-Channel Transistor High Stress Film SiGe SiGe Source: Intel ISS Europe 2009 P. Gargini 7
8 Problem Statement ISS Europe 2009 P. Gargini 8
9 High-k k Dielectric reduces leakage substantially Gate Gate 1.2nm SiO 2 3.0nm High-k Silicon substrate Silicon substrate Benefits compared to current process technologies Capacitance Gate dielectric leakage High-k k vs. SiO 2 60% greater > 100x reduction November 4th, 2003 Benefit Much faster transistors Far cooler ISS Europe 2009 P. Gargini 9 10
10 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology highlights Beyond 32nm Conclusions ISS Europe 2009 P. Gargini 10
11 ISS Europe 2009 IEDM 2007 P. Gargini 11
12 ISS Europe 2009 IEDM 2007 P. Gargini 12
13 ISS Europe 2009 IEDM 2007 P. Gargini 13
14 ISS Europe 2009 IEDM 2007 P. Gargini 14
15 ISS Europe 2009 IEDM 2007 P. Gargini 15
16 ISS Europe 2009 IEDM 2007 P. Gargini 16
17 ISS Europe 2009 IEDM 2007 P. Gargini 17
18 ISS Europe 2009 IEDM 2007 P. Gargini 18
19 ISS Europe 2009 IEDM 2007 P. Gargini 19
20 Scaling trend for inversion electrical TOX Metal Gate (different for NMOS & PMOS) 10 Electrical (Inv) Tox (nm) 1 High-k Silicon Substrate 350nm 250nm 180nm 130nm 90nm 65nm 45nm Gate Leakage (Rel.) ISS Europe 2009 IEDM 2007 P. Gargini 20
21 ISS Europe 2009 P. Gargini 21 IEDM 2007
22 ISS Europe 2009 P. Gargini 22 IEDM 2007
23 ISS Europe 2009 IEDM 2007 P. Gargini 23
24 ISS Europe 2009 P. Gargini 24 IEDM 2007
25 ISS Europe 2009 IEDM 2007 P. Gargini 25
26 ISS Europe 2009 P. Gargini 26 IEDM 2007
27 IEDM 2007 ISS Europe 2009 P. Gargini 27
28 Intel s 45nm Investment FAB INVESTMENT $9B FAB 11X New Mexico FAB 32 Arizona D1D Oregon FAB 28 Israel TECHNOLOGY INVESTMENT $1B 45nm High-k + Metal Gate Transistors SiGe Metal High-k SiGe PRODUCT INVESTMENT $2B Penryn Nehalem Silverthorne Others Source: Intel ISS Europe 2009 P. Gargini 28
29 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology highlights Beyond 32nm Conclusions ISS Europe 2009 P. Gargini 29
30 A 32nm Logic Technology Featuring 2nd-Generation High-k k + Metal-Gate Transistors, Enhanced Channel Strain and 0.171um 2 SRAM Cell Size in a 291Mb Array S. Natarajan,, M. Armstrong, M. Bost, R. Brain, M. Brazier, C-H C H Chang, V. Chikarmane, M. Childs, H. Deshpande, K. Dev, G. Ding, T. Ghani, O. Golonzka, W. Han, J. He*, R. Heussner, R. James, I. Jin, C. Kenyon, K S. Klopcic, S-H. S Lee, M. Liu, S. Lodha, B. McFadden, A. Murthy, L. Neiberg, J. Neirynck, P. Packan, S. Pae*, C. Parker, C. Pelto, L. Pipes, J. Sebastian, J. Seiple, B. Sell, S. Sivakumar, B. Song, K. Tone,, T. Troeger, C. Weber**, M. Yang, A. Yeoh, K. Zhang Logic Technology Development, *QRE, ** TCAD Intel Corporation IEDM 2008 P. Gargini
31 Process Features 32nm Groundrules 193nm Immersion Lithography 2 nd Generation High-K K + Metal Gate 4 th Generation Strained Silicon 9 Cu Interconnect Layers Low-k k CDO / SiCN dielectric Cu bump with Lead-free Packaging ISS Europe 2009 IEDM 2008 P. Gargini 31
32 Contacted Gate Pitch Transistor gate pitch of 112.5nm Continues 0.7x per generation scaling 1000 Contacted Gate Pitch (nm) Pitch 112.5nm Contacted Gate Pitch 0.7x every 2 years nm 180nm 130nm 90nm 65nm 45nm 32nm Technology Node Tightest contacted gate pitch reported for 32nm generation ISS Europe 2009 IEDM 2008 P. Gargini 32
33 SRAM Cells um 2 SRAM cell 10 SRAM Cell Area (um 2 ) 1 SRAM Cell Area 0.5x every 2 years nm 180nm 130nm 90nm 65nm 45nm 32nm Technology Node Transistor density doubles every two years ISS Europe 2009 IEDM 2008 P. Gargini 33
34 SRAM Array Density SRAM array density achieves 4.2 Mb/mm 2 Includes row/column drivers and other circuitry 10.0 SRAM Array Density (Mb/mm 2 ) Mb/mm nm 65nm 45nm 32nm Array density scales at ~2X per generation ISS Europe 2009 IEDM 2008 P. Gargini 34
35 Key Transistor Features 30nm gate length with 112.5nm contacted gate pitch 2 nd generation Hi-k k + Metal Gate 0.9nm EOT Hi-K K with dual workfunction metal gate electrodes Continued use of Replacement Metal Gate approach Metal gate deposition after high temperature anneals Integrated with strained silicon process Transistor mask count same as 45nm Adds ~4% process cost over non hi-k/mg 4 th generation of strained silicon ISS Europe 2009 IEDM 2008 P. Gargini 35
36 NMOS I vs. DSAT I OFF 1000 Vdd=1.0V Ioff (na/um) nm nm 1 45nm: Mistry, 2007 IEDM Idsat (ma/um) 1.55 ma/µm m at I OFF = 100 na/µm 14% better than 45nm ISS Europe 2009 IEDM 2008 P. Gargini 36
37 PMOS I vs. DSAT I OFF 1000 Vdd=1.0V Ioff (na/um) nm: Mistry, 2007 IEDM 45nm nm Idsat (ma/um) 1.31 ma/µm m at I OFF = 100 na/µm 22% better than 45nm 32nm PMOS Idsat almost equal to 45nm NMOS Idsat! ISS Europe 2009 IEDM 2008 P. Gargini 37
38 Transistor Performance vs. Gate Pitch IDSAT (ma/um) V, 100 na/µm 90nm: Mistry, 2004 VLSI 65nm: Tyagi, 2005 IEDM 45nm: Mistry, 2007 IEDM Gate Pitch (Generation) NMOS PMOS 320nm (90nm) 220nm (65nm) Contacted Gate Pitch (nm) 160nm 112.5nm (45nm) (32nm) 100 Highest reported drive current at tightest reported gate pitch Simultaneous performance and density improvement ISS Europe 2009 IEDM 2008 P. Gargini 38
39 Interconnects Metal pitches match transistor pitch Graduated upper level pitches optimize density & performance Extensive use of low-k k ILD and SiCN ISS Europe 2009 IEDM 2008 P. Gargini 39
40 SRAM Yield Defect Density (log scale) 2 Years 32nm SRAM yield maintains 2-year 2 cadence ISS Europe 2009 IEDM 2008 P. Gargini 40
41 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology highlights Beyond 32nm Conclusions ISS Europe 2009 P. Gargini 41
42 Options and Challenges (1) Substrate Engineering (110) vs. (100) crystal orientation + Increased p-channel mobility? Impact on n-channel mobility Hole Mobility (cm 2 /Vs) (100) Mobility (110) Mobility Hole <110> Stress (MPa) <110> (100) <100> <110> <100> (110) <111> <110> ISS Europe 2009 P. Gargini 42
43 Options and Challenges (2) Multi-Gate FETs + Improved electrostatics + Steeper sub-threshold slope? Parasitic resistance? Parasitic capacitance FinFET GAA Wrap around Gate Source-drain Fin ISS Europe 2009 P. Gargini 43
44 Picking the Right High-µ Material Material Property Electron mobility Hole mobility Bandgap (ev) Dielectric constant Si Ge Why Ge? More symmetric and higher carrier mobilities Highest hole mobility Easier integration on Si Lower temperature processing ISS Europe 2009 P. Gargini 44
45 ISS Europe 2009 IEDM 2008 P. Gargini 45
46 Increasing Electron Mobility Increased mobility in the transistor channel leads to higher performance and less energy consumption W IDSAT µ COX L Relative mobility Compound Semiconductors Si GaAs InAs InSb Compound semiconductors have higher electron mobility than Si; InSb (indium antimonide) is highest of all ISS Europe 2009 P. Gargini 46
47 Depletion and Enhancement Mode Gate Source Drain Al x In 1-x Sb barrier InSb QW Source Recessed Gate Al x In 1-x Sb barrier Drain Etch Stop Layer Semi-insulating GaAs substrate for epitaxial growth Semi-insulating GaAs substrate for epitaxial growth Depletion mode (Normally ON) Enhancement mode (Normally OFF) A novel gate recess process is used to fabricate enhancement mode InSb QWFETs IEDM 2005 ISS Europe 2009 P. Gargini 47
48 Speed, Power, Performance Cut-off Frequency, ft [GHz] InSb E-mode QWFET (LG = 85nm) VDS = 0.3V, 0.5V, 0.6V 10X power 1.5X speed Silicon MOSFET (LG = 60nm) VDS = 0.5V, 0.7V, 0.9V, 1.2V DC Power Dissipation [µw/µm] InSb QWFETs show > 10x reduction in active power dissipation compared to Si MOSFETs ISS Europe 2009 P. Gargini 48
49 NMOS 2007 IEDM ISS Europe 2009 P. Gargini 49
50 New Material Integration for High- Performance Transistors N-channel built on Silicon (IEDM 2007) Background: III-V Integration with Silicon Opportunity Higher mobility allows radical voltage scaling for 10x power reduction New material and deposition methods already in use starting with 45nm node Key Challenges Integrate with Silicon Infrastructure Integration with Conventional Design Comparable Density and Cost InGaAs QWFET on Si [L G = 80nm] Si Peak f T > 400GHz at V cc = 0.5V III-V V Transistors May Enable Improved Performance and Lower Power Beyond What Silicon Can Provide Marko Radosavljevic, IEDM 2007 ISS Europe 2009 P. Gargini 50
51 New Material Integration for High- Performance Transistors P-channel with compressive strain (IEDM 2008) Ti/Au Source 6nm p-doped 10nm p-doped 3nm undoped Be δ-doping 7nm undoped Ti/Au Gate L G Ti/Au Drain low resistance cap Alxx In 1-x Sb top barrier Al x In 1-x Sb top barrier Al x In 1-x Sb spacer 5nm InSb quantum well 3 µ m undoped Al x In 1-x Sb bottom barrier 200nm Al y In 1-y S b interfacial layer Semi-insulating GaAs substrate Peak f T > 140 GHz at Vcc = -0.5V High performance III-V p-channel Demonstrated with InSb Compressive strain to raise mobility 10x reduction in power vs equiv Si Highest performance P-channel reported to date Source 40nm gate length Gate Drain P-channel III-V in partnership with Qinetiq Marko Radosavljevic, IEDM 2008 ISS Europe 2009 P. Gargini 51
52 Transistors/Die Intel Sees No End to Moore s s Law 10µm 13 Bipolar PMOS NMOS CMOS Voltage Scaling Data (Moore) Memory Microprocessor Kilo Xtor 1µm 100nm 10nm Mega Xtor Pwr Eff Scaling Giga Xtor New Nano- structures Beyond CMOS? Spin based? Molecular? Other? Tera Xtor ISS Europe 2009 P. Gargini 52
53 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology highlights Beyond 32nm Conclusions ISS Europe 2009 P. Gargini 53
54 Conclusions 45nm and 32nm technologies demonstrate that multiple Technical Red Brick Walls of the past have been overcome Completed development phase on 32nm CMOS On track for production readiness in Q4 09 Multiple viable technical options exist for the next years Device technology will not be a show stopper for the foreseeable future Moore s s Law is Alive and Well! ISS Europe 2009 P. Gargini 54
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