Manufacturing Case Studies: Copy Exactly (CE!) and the two-year cycle at Intel

Size: px
Start display at page:

Download "Manufacturing Case Studies: Copy Exactly (CE!) and the two-year cycle at Intel"

Transcription

1 Manufacturing Case Studies: Copy Exactly (CE!) and the two-year cycle at Intel Paolo A. Gargini Director Technology Strategy Intel Fellow 1

2 Agenda 2-year cycle Copy Exactly Conclusions 2

3 I see no reason to expect the rate of progress In the use of smaller dimensions in complex Circuits to decrease in the near future. With respect to the factor contributed by Device and Circuit Cleverness, however, the situation is different. We are approaching a limit that must slow the rate of progress The new slope might approximate a doubling Every two years. Gordon Moore, IEDM

4 .but Cost of Equipment Continues to Raise (ISMT Exposure Tool Cost Survey Results) Source: ISMT EUV CoO Analysis Update, 1st International EUVL Symposium, October 15th

5 Industry Challenge Introduction of new products into the market place requires very costly investments in research, development and manufacturing. How can an IC company optimize the above phases and obtain maximum return on investment in the shortest time? 5

6 Intel Semiconductor Roadmap 15nm Moore s Law is driving semiconductor technology ~ 30% reduction in transistor size with each new technology every e 2 years ~ 2X more chips per wafer with each new process technology ~ 2X improvement in the product price/performance ratio 6

7 Intel s Core Competencies Drive Processor Performance Silicon Process Transistors Technology 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ (Millions) Intel Brand Pentium Processor 60MHz Pentium II Processor Pentium III Processor Pentium 4 Processor 2GHz+ Northwood 42 + Itanium Processor Madison Deerfield 40 + Process transitions enable: 2x die per wafer, ½ transistor cost, 2x microprocessor speed 7

8 Capital cost per unit wafer area Moderate Cost Increase from Generation to Generation and 300mm Rolls Cost Back 0.35µm 0.25µm 0.18µm 0.13µm 200mm 0.13µm 300mm 8

9 >60X Transistor Cost Drop from 350nm to 90nm Node (Source: Intel 03) Normalized Cost/Transistor Cost per Total Trans 25% Savings/Year 35% Savings/Year 40% Savings/Year nm 250nm 180nm 130nm 90nm Cost/Transistor Normalized to to 130nm Node 2001 Technology Node/Introduction Year

10 Transistor Manufacturing Costs Falling (Source: Sematech 02) Historic -26 % CAGR Accelerated -32 % CAGR Strategic -26 % CAGR Wafer Size Blend 125/150mm 200mm Wafer Size Blend 200mm 300mm Source: Goodall,Randall, et.al., Long-Term Productivity Mechanisms of of the Semiconductor Industry, 9th International Symposium on on Semiconductor Silicon 2002, sponsored by by ECS, International Sematech 10

11 15 years of Is a technology transfer methodology pioneered by Intel The method ensures consistent yield and quality at any Intel factory making the same products The result is highly predictable output from our factories Whether this methodology is suitable for other companies or other industries depends on many factors 11

12 Intel Research, Development and Manufacturing Research Activities are de-centralized Multiple sites, consortia, universities, etc Central Technology Development groups Logic: Hillsboro, Oregon Memory: Santa Clara, California Packaging: Chandler, Arizona from Development into Manufacturing Fastest and Highest Volume Manufacturing Ramp 12

13 Intel s High Volume Manufacturing Sites Washington Systems Mfg. Oregon Dev D1C/D1D Fab 15/20 Board Mfg. California Dev D2 Sub-con Mfg. Arizona Fab12/22 A/T Dev New Mexico Fab 11/11X Colorado Fab 23 Mass. Fab 17 Costa Rica Ireland Fab 14/24 San Jose A/T Brazil Sub-con Mfg. Israel Fab 8/18 Thailand Sub-con Mfg. Malaysia China Pudong A/T Sub-con Mfg. Penang A/T Kulim A/T Kulim Board/Module Mfg. Sub-con Mfg. Taiwan Sub-con Mfg. Philippines Manila A/T Cavite A/T 13

14 Technology Focus: Logic Actual Forecast Process Name P858 Px60 P1262 P1264 P1266 P1268 P st Production Lithography Node nm Gate Length nm Fab Development Research Copy Exactly! Pathfinding 14

15 Huge cumulative investments as volume manufacturing begins 1000x Wafers/Wk 100x Internal Budget 10x 1x External Budget Year Research Development Manufacture Engineers Yield Enhancements 15

16 First Generation! Results Equivalent Yield Development CE! Fab 2nd Fab 3rd Fab Months 16

Vietnam General Manager Intel Corporation

Vietnam General Manager Intel Corporation SHERRY BOGER Biography Ms. Sherry Boger is the General Manager of Intel Products Vietnam and is responsible for the site s ramp of Intel s state-of-the art assembly and test facility located in HCMC. The

More information

Trends and Challenges in VLSI Technology Scaling Towards 100nm

Trends and Challenges in VLSI Technology Scaling Towards 100nm Trends and Challenges in VLSI Technology Scaling Towards 100nm Stefan Rusu Intel Corporation stefan.rusu@intel.com September 2001 Stefan Rusu 9/2001 2001 Intel Corp. Page 1 Agenda VLSI Technology Trends

More information

Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells

Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells Intel's 65 nm Logic Technology Demonstrated on 0.57 µm 2 SRAM Cells Mark Bohr Intel Senior Fellow Director of Process Architecture & Integration Intel 1 What are We Announcing? Intel has fabricated fully-functional

More information

The future of lithography and its impact on design

The future of lithography and its impact on design The future of lithography and its impact on design Chris Mack www.lithoguru.com 1 Outline History Lessons Moore s Law Dennard Scaling Cost Trends Is Moore s Law Over? Litho scaling? The Design Gap The

More information

Progress due to: Feature size reduction - 0.7X/3 years (Moore s Law). Increasing chip size - 16% per year. Creativity in implementing functions.

Progress due to: Feature size reduction - 0.7X/3 years (Moore s Law). Increasing chip size - 16% per year. Creativity in implementing functions. Introduction - Chapter 1 Evolution of IC Fabrication 1960 and 1990 integrated t circuits. it Progress due to: Feature size reduction - 0.7X/3 years (Moore s Law). Increasing chip size - 16% per year. Creativity

More information

450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D

450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D 450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D Doug Anberg VP, Technical Marketing Ultratech SOKUDO Lithography Breakfast Forum July 10, 2013 Agenda Next Generation Technology

More information

Intel Technology Journal

Intel Technology Journal Volume 06 Issue 02 Published, May 16, 2002 ISSN 1535766X Intel Technology Journal Semiconductor Technology and Manufacturing The Intel Lithography Roadmap A compiled version of all papers from this issue

More information

The SEMATECH Model: Potential Applications to PV

The SEMATECH Model: Potential Applications to PV Continually cited as the model for a successful industry/government consortium Accelerating the next technology revolution The SEMATECH Model: Potential Applications to PV Dr. Michael R. Polcari President

More information

Used Semiconductor Manufacturing Equipment: Looking for Sales in All the Right Places. Study Number MA108-09

Used Semiconductor Manufacturing Equipment: Looking for Sales in All the Right Places. Study Number MA108-09 Study Number MA108-09 August 2009 Copyright Semico Research, 2009. All rights reserved. Reproduction in whole or part is prohibited without permission of Semico. The contents of this report represent

More information

Semiconductor Industry Perspective

Semiconductor Industry Perspective Semiconductor Industry Perspective National Academy of Engineering Workshop on the Offshoring of Engineering Washington, D.C. October 25, 2006 Dr. Robert Doering Texas Instruments, Inc. A Few Introductory

More information

Introduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Introduction. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 1 What is this book all about? Introduction to digital integrated circuits.

More information

32nm Technology and Beyond

32nm Technology and Beyond 32nm Technology and Beyond Paolo Gargini Chairman ITRS IEEE Fellow Director of Technology Strategy Intel Fellow ISS Europe 2009 P. Gargini 1 Agenda Equivalent Scaling 45nm Technology summary 32nm Technology

More information

TWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm

TWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm TWINSCAN XT:1950i Water-based immersion taken to the max Enabling fast, single-exposure lithography at sub 40 nm SEMICON West, San Francisco July 14-18, 2008 Slide 1 The immersion pool becomes an ocean

More information

Intel Demonstrates High-k + Metal Gate Transistor Breakthrough on 45 nm Microprocessors

Intel Demonstrates High-k + Metal Gate Transistor Breakthrough on 45 nm Microprocessors Intel Demonstrates High-k + Metal Gate Transistor Breakthrough on 45 nm Microprocessors Mark Bohr Intel Senior Fellow Logic Technology Development Kaizad Mistry 45 nm Program Manager Logic Technology Development

More information

1 Digital EE141 Integrated Circuits 2nd Introduction

1 Digital EE141 Integrated Circuits 2nd Introduction Digital Integrated Circuits Introduction 1 What is this lecture about? Introduction to digital integrated circuits + low power circuits Issues in digital design The CMOS inverter Combinational logic structures

More information

Introduction to VLSI ASIC Design and Technology

Introduction to VLSI ASIC Design and Technology Introduction to VLSI ASIC Design and Technology Paulo Moreira CERN - Geneva, Switzerland Paulo Moreira Introduction 1 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics

More information

EMT 251 Introduction to IC Design

EMT 251 Introduction to IC Design EMT 251 Introduction to IC Design (Pengantar Rekabentuk Litar Terkamir) Semester II 2011/2012 Introduction to IC design and Transistor Fundamental Some Keywords! Very-large-scale-integration (VLSI) is

More information

2010 IRI Annual Meeting R&D in Transition

2010 IRI Annual Meeting R&D in Transition 2010 IRI Annual Meeting R&D in Transition U.S. Semiconductor R&D in Transition Dr. Peter J. Zdebel Senior VP and CTO ON Semiconductor May 4, 2010 Some Semiconductor Industry Facts Founded in the U.S. approximately

More information

PC accounts for 353 Cory will be created early next week (when the class list is completed) Discussions & Labs start in Week 3

PC accounts for 353 Cory will be created early next week (when the class list is completed) Discussions & Labs start in Week 3 EE141 Fall 2005 Lecture 2 Design Metrics Admin Page Everyone should have a UNIX account on Cory! This will allow you to run HSPICE! If you do not have an account, check: http://www-inst.eecs.berkeley.edu/usr/

More information

Competitive in Mainstream Products

Competitive in Mainstream Products Competitive in Mainstream Products Bert Koek VP, Business Unit manager 300mm Fabs Analyst Day 20 September 2005 ASML Competitive in mainstream products Introduction Market share Device layers critical

More information

W ith development risk fully borne by the equipment industry and a two-year delay in the main

W ith development risk fully borne by the equipment industry and a two-year delay in the main Page 1 of 5 Economic Challenges and Opportunities in the 300 mm Transition Iddo Hadar, Jaim Nulman, Kunio Achiwa, and Oded Turbahn, Applied Materials Inc. -- 10/1/1998 Semiconductor International W ith

More information

G450C. Global 450mm Consortium at CNSE. Michael Liehr, General Manager G450C, Vice President for Research

G450C. Global 450mm Consortium at CNSE. Michael Liehr, General Manager G450C, Vice President for Research Global 450mm Consortium at CNSE Michael Liehr, General Manager G450C, Vice President for Research - CNSE Overview - G450C Vision - G450C Mission - Org Structure - Scope - Timeline The Road Ahead for Nano-Fabrication

More information

ISSCC 2003 / SESSION 1 / PLENARY / 1.1

ISSCC 2003 / SESSION 1 / PLENARY / 1.1 ISSCC 2003 / SESSION 1 / PLENARY / 1.1 1.1 No Exponential is Forever: But Forever Can Be Delayed! Gordon E. Moore Intel Corporation Over the last fifty years, the solid-state-circuits industry has grown

More information

Copyright 2003 by the Society of Photo-Optical Instrumentation Engineers.

Copyright 2003 by the Society of Photo-Optical Instrumentation Engineers. Copyright 2003 by the Society of Photo-Optical Instrumentation Engineers. This paper was published in the proceedings of Optical Microlithography XVI, SPIE Vol. 5040, pp. xxi-xxxi. It is made available

More information

Economic Model Workshop, Philadelphia

Economic Model Workshop, Philadelphia Economic Model Workshop, Philadelphia Denis Fandel, Project Manager, MM&P 1 August 2001 Meeting Guidelines Project Mission / Model Overview Early Production Test Program Fundamental Assumption Allocation

More information

EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING

EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING EMERGING SUBSTRATE TECHNOLOGIES FOR PACKAGING Henry H. Utsunomiya Interconnection Technologies, Inc. Suwa City, Nagano Prefecture, Japan henryutsunomiya@mac.com ABSTRACT This presentation will outline

More information

ISMI Industry Productivity Driver

ISMI Industry Productivity Driver SEMATECH Symposium Japan September 15, 2010 Accelerating Manufacturing Productivity ISMI Industry Productivity Driver Scott Kramer VP Manufacturing Technology SEMATECH Copyright 2010 SEMATECH, Inc. SEMATECH,

More information

Scaling of Semiconductor Integrated Circuits and EUV Lithography

Scaling of Semiconductor Integrated Circuits and EUV Lithography Scaling of Semiconductor Integrated Circuits and EUV Lithography ( 半導体集積回路の微細化と EUV リソグラフィー ) December 13, 2016 EIDEC (Emerging nano process Infrastructure Development Center, Inc.) Hidemi Ishiuchi 1 OUTLINE

More information

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Introduction

Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, Digital EE141 Integrated Circuits 2nd Introduction Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002 1 What is this book all about? Introduction to digital integrated circuits.

More information

It s Time for 300mm Prime

It s Time for 300mm Prime It s Time for 300mm Prime Iddo Hadar Managing Director, 300mm Prime Program Office SEMI Strategic Business Conference Napa Valley, California Tuesday, April 24, 2007 Safe Harbor Statement This presentation

More information

Lithography Industry Collaborations

Lithography Industry Collaborations Accelerating the next technology revolution Lithography Industry Collaborations SOKUDO Breakfast July 13, 2011 Stefan Wurm SEMATECH Copyright 2009 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered

More information

Multiple Patterning for Immersion Extension and EUV Insertion. Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group

Multiple Patterning for Immersion Extension and EUV Insertion. Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group Multiple Patterning for Immersion Extension and EUV Insertion Chris Bencher Distinguished Member of Technical Staff Applied Materials CTO group Abstract Multiple Patterning for Immersion Extension and

More information

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm EE241 - Spring 20 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements No office hour next Monday Extra office hour Tuesday 2-3pm 2 1 Outline

More information

Advancing Industry Productivity

Advancing Industry Productivity Advancing Industry Productivity Iddo Hadar Joint Productivity Working Group Session Austin, Texas Thursday, October 12, 2006 F O U N D A T I O N E N G I N E E R I N G G R O U P Safe Harbor Statement This

More information

In 1951 William Shockley developed the world first junction transistor. One year later Geoffrey W. A. Dummer published the concept of the integrated

In 1951 William Shockley developed the world first junction transistor. One year later Geoffrey W. A. Dummer published the concept of the integrated Objectives History and road map of integrated circuits Application specific integrated circuits Design flow and tasks Electric design automation tools ASIC project MSDAP In 1951 William Shockley developed

More information

Practical Information

Practical Information EE241 - Spring 2010 Advanced Digital Integrated Circuits TuTh 3:30-5pm 293 Cory Practical Information Instructor: Borivoje Nikolić 550B Cory Hall, 3-9297, bora@eecs Office hours: M 10:30am-12pm Reader:

More information

Practical Information

Practical Information EE241 - Spring 2013 Advanced Digital Integrated Circuits MW 2-3:30pm 540A/B Cory Practical Information Instructor: Borivoje Nikolić 509 Cory Hall, 3-9297, bora@eecs Office hours: M 11-12, W 3:30pm-4:30pm

More information

Intel s s Silicon Power Savings Strategy

Intel s s Silicon Power Savings Strategy Intel s s Silicon Power Savings Strategy Keeping Moore s s Law Alive and Well Paolo Gargini Intel Fellow and Director, Technology Strategy Agenda Moore s s Law and scaling The power challenge Looking ahead

More information

A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors

A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann*, K. Johnson#,

More information

Silicon VLSI Technology. Fundamentals, Practice and Modeling. Class Notes For Instructors. J. D. Plummer, M. D. Deal and P. B.

Silicon VLSI Technology. Fundamentals, Practice and Modeling. Class Notes For Instructors. J. D. Plummer, M. D. Deal and P. B. Silicon VLSI Technology Fundamentals, ractice, and Modeling Class otes For Instructors J. D. lummer, M. D. Deal and. B. Griffin These notes are intended to be used for lectures based on the above text.

More information

A Perspective on Semiconductor Equipment. R. B. Herring March 4, 2004

A Perspective on Semiconductor Equipment. R. B. Herring March 4, 2004 A Perspective on Semiconductor Equipment R. B. Herring March 4, 2004 Outline Semiconductor Industry Overview of circuit fabrication Semiconductor Equipment Industry Some equipment business strategies Product

More information

Enabling Semiconductor Innovation and Growth

Enabling Semiconductor Innovation and Growth Enabling Semiconductor Innovation and Growth EUV lithography drives Moore s law well into the next decade BAML 2018 APAC TMT Conference Taipei, Taiwan Craig De Young Vice President IR - Asia IR March 14,

More information

Recent Trends in Semiconductor IC Device Manufacturing

Recent Trends in Semiconductor IC Device Manufacturing Recent Trends in Semiconductor IC Device Manufacturing August 2007 Dr. Stephen Daniels Executive Director National Centre for Plasma Moore s Law Moore s First Law Chip Density will double ever 18months.

More information

Chapter 1, Introduction

Chapter 1, Introduction Introduction to Semiconductor Manufacturing Technology Chapter 1, Introduction hxiao89@hotmail.com 1 Objective After taking this course, you will able to Use common semiconductor terminology Describe a

More information

(Complementary E-Beam Lithography)

(Complementary E-Beam Lithography) Extending Optical Lithography with C E B L (Complementary E-Beam Lithography) July 13, 2011 4008 Burton Drive, Santa Clara, CA 95054 Outline Complementary Lithography E-Beam Complements Optical Multibeam

More information

EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141

EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141 EECS 151/251A Spring 2019 Digital Design and Integrated Circuits Instructors: Wawrzynek Lecture 8 EE141 From the Bottom Up IC processing CMOS Circuits (next lecture) EE141 2 Overview of Physical Implementations

More information

Systems with Digital Integrated Circuits

Systems with Digital Integrated Circuits Systems with Digital Integrated Circuits Introduction Sorin Hintea Basis of Electronics Departament Commutative logic The operation of digital circuits is based on the use of switches capable of going

More information

Overview of Design Methodology. A Few Points Before We Start 11/4/2012. All About Handling The Complexity. Lecture 1. Put things into perspective

Overview of Design Methodology. A Few Points Before We Start 11/4/2012. All About Handling The Complexity. Lecture 1. Put things into perspective Overview of Design Methodology Lecture 1 Put things into perspective ECE 156A 1 A Few Points Before We Start ECE 156A 2 All About Handling The Complexity Design and manufacturing of semiconductor products

More information

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

Lecture 1: Introduction to Digital System Design & Co-Design

Lecture 1: Introduction to Digital System Design & Co-Design Design & Co-design of Embedded Systems Lecture 1: Introduction to Digital System Design & Co-Design Computer Engineering Dept. Sharif University of Technology Winter-Spring 2008 Mehdi Modarressi Topics

More information

450mm silicon wafers specification challenges. Mike Goldstein Intel Corp.

450mm silicon wafers specification challenges. Mike Goldstein Intel Corp. 450mm silicon wafers specification challenges Mike Goldstein Intel Corp. Outline Background 450mm transition program 450mm silicon evolution Mechanical grade wafers (spec case study) Developmental (test)

More information

Energy beam processing and the drive for ultra precision manufacturing

Energy beam processing and the drive for ultra precision manufacturing Energy beam processing and the drive for ultra precision manufacturing An Exploration of Future Manufacturing Technologies in Response to the Increasing Demands and Complexity of Next Generation Smart

More information

PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS. LUC VAN DEN HOVE President & CEO imec

PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS. LUC VAN DEN HOVE President & CEO imec PUSHING LITHOGRAPHY TO ENABLE ULTIMATE NANO-ELECTRONICS LUC VAN DEN HOVE President & CEO imec OUTLINE! Industry drivers! Roadmap extension! Lithography options! Innovation through global collaboration

More information

The Road to 450 mm Semiconductor Wafers Ira Feldman

The Road to 450 mm Semiconductor Wafers Ira Feldman The Road to 450 mm Semiconductor Wafers Ira Feldman Feldman Engineering Corp. Why 450 mm Wafers? Technical Challenges Economic Challenges Solutions Summary Overview 2 the number of transistors on a chip

More information

Digital Integrated Circuits

Digital Integrated Circuits Digital Integrated Circuits Yaping Dan ( 但亚平 ), PhD Office: Law School North 301 Tel: 34206045-3011 Email: yapingd@gmail.com Digital Integrated Circuits Introduction p-n junctions and MOSFETs The CMOS

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

Story. Cover. R e d e fining Moore s Law

Story. Cover. R e d e fining Moore s Law Cover Story R e d e fining Moore s Law Chris A. Mack, KLA-Tencor Corporation The economic drivers of Moore s Law can be divided into push drivers and pull drivers. Push drivers are the technology innovations

More information

Wafer Test and Yield Analysis

Wafer Test and Yield Analysis Wafer Test and Yield Analysis This program is sponsored by: Kulim Hi-Tech Park Conducted by: DreamCatcher Consulting Sdn Bhd Wafer Test and Yield Analysis SYPNOSIS Wafer yield has always been an important

More information

Integrated Circuit Technology (Course Code: EE662) Lecture 1: Introduction

Integrated Circuit Technology (Course Code: EE662) Lecture 1: Introduction Indian Institute of Technology Jodhpur, Year 2015 2016 Integrated Circuit Technology (Course Code: EE662) Lecture 1: Introduction Course Instructor: Shree Prakash Tiwari, Ph.D. Email: sptiwari@iitj.ac.in

More information

Chapter 3 Digital Logic Structures

Chapter 3 Digital Logic Structures Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2000): 48 million IBM PowerPC 750FX (2002): 38 million IBM/Apple

More information

Low Power Design of Successive Approximation Registers

Low Power Design of Successive Approximation Registers Low Power Design of Successive Approximation Registers Rabeeh Majidi ECE Department, Worcester Polytechnic Institute, Worcester MA USA rabeehm@ece.wpi.edu Abstract: This paper presents low power design

More information

AN ANALYSIS: TRADITIONAL SEMICONDUCTOR LITHOGRAPHY VERSUS EMERGING TECHNOLOGY (NANO IMPRINT) Robert L. Wright Kranthi Mitra Adusumilli

AN ANALYSIS: TRADITIONAL SEMICONDUCTOR LITHOGRAPHY VERSUS EMERGING TECHNOLOGY (NANO IMPRINT) Robert L. Wright Kranthi Mitra Adusumilli Proceedings of the 2005 Winter Simulation Conference M. E. Kuhl, N. M. Steiger, F. B. Armstrong, and J. A. Joines, eds. AN ANALYSIS: TRADITIONAL SEMICONDUCTOR LITHOGRAPHY VERSUS EMERGING TECHNOLOGY (NANO

More information

Market and technology trends in advanced packaging

Market and technology trends in advanced packaging Close Market and technology trends in advanced packaging Executive OVERVIEW Recent advances in device miniaturization trends have placed stringent requirements for all aspects of product manufacturing.

More information

Photoresists & Ancillaries. Materials for Semiconductor Manufacturing A TECHCET Critical Materials Report

Photoresists & Ancillaries. Materials for Semiconductor Manufacturing A TECHCET Critical Materials Report 2018-19 Photoresists & Ancillaries Materials for Semiconductor Manufacturing A TECHCET Critical Materials Report Prepared by Ed Korczynski Reviewed and Edited by Lita Shon-Roy TECHCET CA LLC PO Box 3814

More information

Doug Dunn ASML President and Chief Executive Officer Deutsche Bank Conference London, England September 19, / Slide 1

Doug Dunn ASML President and Chief Executive Officer Deutsche Bank Conference London, England September 19, / Slide 1 Doug Dunn ASML President and Chief Executive Officer Deutsche Bank Conference London, England September 19, 2003 / Slide 1 Safe Harbor Safe Harbor Statement under the U.S. Private Securities Litigation

More information

Through-Silicon-Via Inductor: Is it Real or Just A Fantasy?

Through-Silicon-Via Inductor: Is it Real or Just A Fantasy? Through-Silicon-Via Inductor: Is it Real or Just A Fantasy? Umamaheswara Rao Tida 1 Cheng Zhuo 2 Yiyu Shi 1 1 ECE Department, Missouri University of Science and Technology 2 Intel Research, Hillsboro Outline

More information

MAPPER: High throughput Maskless Lithography

MAPPER: High throughput Maskless Lithography MAPPER: High throughput Maskless Lithography Marco Wieland CEA- Leti Alterative Lithography workshop 1 Today s agenda Introduction Applications Qualification of on-tool metrology by in-resist metrology

More information

Lecture 1 Introduction to Electronic

Lecture 1 Introduction to Electronic Lecture 1 Introduction to Electronic Present by : Thawatchai Thongleam Faculty of Science and Technology Nakhon Pathom Rajabhat Uniersity Electronic Engineering Lecture 1 Introduction to Electronic Lecture

More information

Transistor Scaling in the Innovation Era. Mark Bohr Intel Senior Fellow Logic Technology Development August 15, 2011

Transistor Scaling in the Innovation Era. Mark Bohr Intel Senior Fellow Logic Technology Development August 15, 2011 Transistor Scaling in the Innovation Era Mark Bohr Intel Senior Fellow Logic Technology Development August 15, 2011 MOSFET Scaling Device or Circuit Parameter Scaling Factor Device dimension tox, L, W

More information

MEMS On-wafer Evaluation in Mass Production Testing At the Earliest Stage is the Key to Lowering Costs

MEMS On-wafer Evaluation in Mass Production Testing At the Earliest Stage is the Key to Lowering Costs MEMS On-wafer Evaluation in Mass Production Testing At the Earliest Stage is the Key to Lowering Costs Application Note Recently, various devices using MEMS technology such as pressure sensors, accelerometers,

More information

MICROPROCESSOR TECHNOLOGY

MICROPROCESSOR TECHNOLOGY MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 3 Ch.1 The Evolution of The Microprocessor 17-Feb-15 1 Chapter Objectives Introduce the microprocessor evolution from transistors to

More information

CMOS Process Variations: A Critical Operation Point Hypothesis

CMOS Process Variations: A Critical Operation Point Hypothesis CMOS Process Variations: A Critical Operation Point Hypothesis Janak H. Patel Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign jhpatel@uiuc.edu Computer Systems

More information

Technology & Manufacturing

Technology & Manufacturing Technology & Manufacturing Jean-Marc Chery Chief Operating Officer Front-End Manufacturing Unique capability 2 Technology portfolio aligned with application focus areas Flexible IDM model with foundry

More information

Optical lithography is the technique for

Optical lithography is the technique for By Chris A. Mack Snapshot: The author describes optical lithography in the context of the semiconductor industry. Past trends are evaluated and used to predict future possibilities. The economics of the

More information

FinFET vs. FD-SOI Key Advantages & Disadvantages

FinFET vs. FD-SOI Key Advantages & Disadvantages FinFET vs. FD-SOI Key Advantages & Disadvantages Amiad Conley Technical Marketing Manager Process Diagnostics & Control, Applied Materials ChipEx-2014, Apr 2014 1 Moore s Law The number of transistors

More information

HOW TO CONTINUE COST SCALING. Hans Lebon

HOW TO CONTINUE COST SCALING. Hans Lebon HOW TO CONTINUE COST SCALING Hans Lebon OUTLINE Scaling & Scaling Challenges Imec Technology Roadmap Wafer size scaling : 450 mm 2 COST SCALING IMPROVED PERFORMANCE 3 GLOBAL TRAFFIC FORECAST Cloud Traffic

More information

Kenneth R. Laker, University of Pennsylvania, updated 20Jan15

Kenneth R. Laker, University of Pennsylvania, updated 20Jan15 http://www.seas.upenn.edu/~ese570/ 1 TOPICS The Course Industry Trends Digital CMOS Basics Some VLSI Fundamentals Illustrative Design Example 2 1. Apply principles of hierarchical digital CMOS VLSI, from

More information

DUV. Matthew McLaren Vice President Program Management, DUV. 24 November 2014

DUV. Matthew McLaren Vice President Program Management, DUV. 24 November 2014 DUV Matthew McLaren Vice President Program Management, DUV 24 Forward looking statements This document contains statements relating to certain projections and business trends that are forward-looking,

More information

Pierre Brondeau Vice President, Business Group Executive Electronic Materials Regional Director - Europe Lehman Brothers Conference Call November

Pierre Brondeau Vice President, Business Group Executive Electronic Materials Regional Director - Europe Lehman Brothers Conference Call November Pierre Brondeau Vice President, Business Group Executive Electronic Materials Regional Director - Europe Lehman Brothers Conference Call November 2006 Forward Looking Statement The presentation today may

More information

ASML Market dynamics. Dave Chavoustie EVP Sales Analyst Day, September 30, 2004

ASML Market dynamics. Dave Chavoustie EVP Sales Analyst Day, September 30, 2004 ASML Market dynamics Dave Chavoustie EVP Sales Analyst Day, September 30, 2004 Agenda! Market Overview! Growth Opportunities! 300mm Market! Asia Overview / Slide 2 ASML Unit Market Share Trend 60% 12 &

More information

Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference

Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference Craig De Young Vice President Investor Relations Taipei, Taiwan March 12, 2013 Forward looking statements Slide 2 Safe Harbor Statement

More information

CS 6135 VLSI Physical Design Automation Fall 2003

CS 6135 VLSI Physical Design Automation Fall 2003 CS 6135 VLSI Physical Design Automation Fall 2003 1 Course Information Class time: R789 Location: EECS 224 Instructor: Ting-Chi Wang ( ) EECS 643, (03) 5742963 tcwang@cs.nthu.edu.tw Office hours: M56R5

More information

From Sand to Silicon Making of a Chip Illustrations May 2009

From Sand to Silicon Making of a Chip Illustrations May 2009 From Sand to Silicon Making of a Chip Illustrations May 2009 1 The illustrations on the following foils are low resolution images that visually support the explanations of the individual steps. For publishing

More information

Public. Introduction to ASML. Ron Kool. SVP Corporate Strategy and Marketing. March-2015 Veldhoven

Public. Introduction to ASML. Ron Kool. SVP Corporate Strategy and Marketing. March-2015 Veldhoven Public Introduction to ASML Ron Kool SVP Corporate Strategy and Marketing March-2015 Veldhoven 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012

More information

Leakage Current in Low Standby Power and High Performance Devices: Trends and Challenges

Leakage Current in Low Standby Power and High Performance Devices: Trends and Challenges Leakage Current in Low Standby Power and High Performance Devices: Trends and Challenges (Invited Paper) Geoffrey C-F Yeap Motorola Inc., DigitalDNA Laboratories, 3501 Ed Bluestein Blvd., MD: K10, Austin,

More information

6.012 Microelectronic Devices and Circuits

6.012 Microelectronic Devices and Circuits MIT, Spring 2003 6.012 Microelectronic Devices and Circuits Jesús del Alamo Dimitri Antoniadis, Judy Hoyt, Charles Sodini Pablo Acosta, Susan Luschas, Jorg Scholvin, Niamh Waldron Lecture 1 6.012 overview

More information

Statistical Static Timing Analysis Technology

Statistical Static Timing Analysis Technology Statistical Static Timing Analysis Technology V Izumi Nitta V Toshiyuki Shibuya V Katsumi Homma (Manuscript received April 9, 007) With CMOS technology scaling down to the nanometer realm, process variations

More information

Semiconductor Devices

Semiconductor Devices Semiconductor Devices - 2014 Lecture Course Part of SS Module PY4P03 Dr. P. Stamenov School of Physics and CRANN, Trinity College, Dublin 2, Ireland Hilary Term, TCD 3 th of Feb 14 MOSFET Unmodified Channel

More information

Agenda. Digital Today Smart Power Management Tomorrow. Brief History of transistor development. Analog PWM controllers. CMOS Historical perspective

Agenda. Digital Today Smart Power Management Tomorrow. Brief History of transistor development. Analog PWM controllers. CMOS Historical perspective 6-Sep-06 Digital Today Smart Power Management Tomorrow September 2006 Stephen Pullen Vice President System Engineering Primarion Corporation Agenda o o o o o o Brief History of transistor development Analog

More information

Lecture 1 Introduction to Solid State Electronics

Lecture 1 Introduction to Solid State Electronics EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 1 Introduction to Solid State Electronics Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology

More information

Probabilistic and Variation- Tolerant Design: Key to Continued Moore's Law. Tanay Karnik, Shekhar Borkar, Vivek De Circuit Research, Intel Labs

Probabilistic and Variation- Tolerant Design: Key to Continued Moore's Law. Tanay Karnik, Shekhar Borkar, Vivek De Circuit Research, Intel Labs Probabilistic and Variation- Tolerant Design: Key to Continued Moore's Law Tanay Karnik, Shekhar Borkar, Vivek De Circuit Research, Intel Labs 1 Outline Variations Process, supply voltage, and temperature

More information

POSSUM TM Die Design as a Low Cost 3D Packaging Alternative

POSSUM TM Die Design as a Low Cost 3D Packaging Alternative POSSUM TM Die Design as a Low Cost 3D Packaging Alternative The trend toward 3D system integration in a small form factor has accelerated even more with the introduction of smartphones and tablets. Integration

More information

NO COST APPLICATIONS FOR ASSEMBLY CYCLE TIME REDUCTION

NO COST APPLICATIONS FOR ASSEMBLY CYCLE TIME REDUCTION NO COST APPLICATIONS FOR ASSEMBLY CYCLE TIME REDUCTION Steven Brown, Joerg Domaschke, and Franz Leibl Siemens AG, HL MS Balanstrasse 73 Munich 81541, Germany email: steven.brown@siemens-scg.com KEY WORDS

More information

Static Power and the Importance of Realistic Junction Temperature Analysis

Static Power and the Importance of Realistic Junction Temperature Analysis White Paper: Virtex-4 Family R WP221 (v1.0) March 23, 2005 Static Power and the Importance of Realistic Junction Temperature Analysis By: Matt Klein Total power consumption of a board or system is important;

More information

Intel Technology Journal

Intel Technology Journal Volume 06 Issue 02 Published, May 16, 2002 ISSN 1535766X Intel Technology Journal Semiconductor Technology and Manufacturing This issue of the Intel Technology Journal describes Intel's state-of-the-art

More information

NANOELECTRONIC TECHNOLOGY: CHALLENGES IN THE 21st CENTURY

NANOELECTRONIC TECHNOLOGY: CHALLENGES IN THE 21st CENTURY NANOELECTRONIC TECHNOLOGY: CHALLENGES IN THE 21st CENTURY S. M. SZE National Chiao Tung University Hsinchu, Taiwan And Stanford University Stanford, California ELECTRONIC AND SEMICONDUCTOR INDUSTRIES

More information

Keysight Technologies MEMS On-wafer Evaluation in Mass Production

Keysight Technologies MEMS On-wafer Evaluation in Mass Production Keysight Technologies MEMS On-wafer Evaluation in Mass Production Testing at the Earliest Stage is the Key to Lowering Costs Application Note Introduction Recently, various devices using MEMS technology

More information

ELCN100 Electronic Lab. Instruments and Measurements Spring Lecture 01: Introduction

ELCN100 Electronic Lab. Instruments and Measurements Spring Lecture 01: Introduction ELCN100 Electronic Lab. Instruments and Measurements Spring 2018 Lecture 01: Introduction Dr. Hassan Mostafa حسن مصطفى د. hmostafa@uwaterloo.ca LAB 1 Cairo University Course Outline Course objectives To

More information

Reducing Transistor Variability For High Performance Low Power Chips

Reducing Transistor Variability For High Performance Low Power Chips Reducing Transistor Variability For High Performance Low Power Chips HOT Chips 24 Dr Robert Rogenmoser Senior Vice President Product Development & Engineering 1 HotChips 2012 Copyright 2011 SuVolta, Inc.

More information

MASK COST OF OWNERSHIP OF EXTREME ULTRAVIOLET LITHOGRAPHY VERSUS 193nm DOUBLE PATTERNING

MASK COST OF OWNERSHIP OF EXTREME ULTRAVIOLET LITHOGRAPHY VERSUS 193nm DOUBLE PATTERNING MASK COST OF OWNERSHIP OF EXTREME ULTRAVIOLET LITHOGRAPHY VERSUS 193nm DOUBLE PATTERNING Presented to The Faculty of the Department of General Engineering San Jose State University In Partial Fulfillment

More information