Intel s s Silicon Power Savings Strategy

Transcription

1 Intel s s Silicon Power Savings Strategy Keeping Moore s s Law Alive and Well Paolo Gargini Intel Fellow and Director, Technology Strategy

2 Agenda Moore s s Law and scaling The power challenge Looking ahead 2

3 Agenda Moore s s Law and scaling The power challenge Looking ahead 3

4 Moore s Law Moore s s Law Transistors Per Die The new slope might approxi- mate a doubling every two years, rather than every year, by the end of the decade. Gordon Moore, 1975 Reduced cost is one of the big attractions of integrated electronics, and the cost advantage continues to increase as the technology evolves toward the production of larger and larger circuit functions on a single semiconductor substrate. Electronics, Volume 38, Number 8, April 19, Data (Moore) Source: Intel 4

5 Processor Moore s s Law (functions per chip) Pentium Processor 286 Itanium 2 Processor Itanium Processor Pentium III Processor 486 DX Processor 2X/2YR Pentium 4 Processor Pentium II Processor 2X/1YR 2X/2YR ,000,000,000 1,000,000, ,000,000 10,000,000 1,000, ,000 10,000 1,000 5

6 Moore s Law Moore s s Law in Action: Intel 486 Processor Microprocessors Advance 1.0µm 0.8µm 0.6µm 0.35µm 0.25µm 0.18µm 0.13µm 90nm Pentium Processor Pentium II/III Processor Pentium 4 Processor Process + architecture innovations 6 Source: Intel

7 Manufacturing Leadership: Scale, Agility and Excellence 0.13 µm 90 nm Wafer Starts / Week (200mm Equiv.) 0.6 µm 0.35 µm 0.25 µm 0.18 µm 65 nm Each process generation ramps faster and higher 7

8 Intel s s 90nm Process Yield Improved at Record Rate 0.18µm 200mm 0.13 µm 200mm 0.13 µm 300mm 90nm 300mm Defect Density (log scale) Source: Intel 8

9 Average Transistor Price by Year Nearly 7 Orders Of Magnitude Reduction in Price/Transistor Nanodollars per transistor! '68 '70 '72 '74 '76 '78 '80 '82 '84 '86 '88 '90 '92 '94 '96 '98 '00 '02 Source: WSTS/Dataquest/Intel, 3/04 9

10 Silicon Technology Reaches Nanoscale 10 Nominal feature size Micron Gate Length Nanotechnology (< 100nm) 0.7X every 2 years 130nm 90nm 65nm 45nm 32nm 70nm 22nm 50nm 35nm 25nm 18nm 12nm Nano- meter Source: Intel 10

11 Lithography Must Break Through to Shorter Wavelength 13.5nm) Looking ahead 1000 nm Feature size * Extreme Ultraviolet 100 Lithography Wavelength 248nm 193nm & extensions Gap EUV Source: Intel 11

12 Environm ent, Safety, and Health im pact reduction: safer solvents, w ater soluble, dry processing, etc. H igh sensitivity alternate chem istries (Non-acid catalyzed) I-L in e 248 nm DU V 0.35 m m G e n e r a tio n 248 nm DU V w/ enhancem ents 1X X-ray single layer 0.25 um Generation n m s i n g l e l a y e r & A R C RESIST TECHNOLOGY EUV n m s i n g l e l a y e r & A R C n m s u r f a c e i m a g i n g 1 X X - r a y s i n g l e l a y e r 193 nm N X I o n p r o j e c t i o n N X E-beam projection N X E-beam projection N X Ion Projection E-beam high th ro u g p u t N a r r o w o p t i o n s t o o l - b a s e d N a r r o w O p t i o n s t o o l - b a s e d 0.18 um Generation 0.10 um G e n e r a tio n A dvanced R esist S y s t e m s 1X X-ray E U V N X E-beam projection NX Ion Projection E-beam high througput N a r r o w O p t i o n s t o o l - b a s e d 0.10 um Generation 1X X-ray L e a d in g - E d g e P r o d u c t io n P ilo t L in e Further Study Required D e v e lo p m e n t / M o s t L ik e ly P a th B a c k U p Figure 14 Critical Level Resist Technology Potential Solutions Roadmap 1994 NTRS Semiconductor Industry Association. The National Technology Roadmap for Semiconductors, 1994 edition. SEMATECH:Austin, Tx,

13 Looking ahead EUV Lithography in Commercial Development EUV Micro exposure tool (MET) EUV MET Image (8/04) Integrated development in progress Source power and lifetime Defect free mask fabrication and handling Optics lifetime Resist performance Source: Intel 13

14 Looking ahead EUV Source Power Increased EUV Power at Intermediate Focus [W] W Production Requirement Average of reported data (SEMATECH Source Workshops) Exponential fit to data Jul-01 Jan-02 Jul-02 Jan-03 Jul-03 Jan-04 Jul-04 Jan-05 Jul-05 Jan-06 Source: SEMATECH 14

15 Looking ahead EUV Mask Blank Defects Reduced 1 Results from SEMATECH Process added defect sensitivity (cm-2) Goal Target for 32nm Only 1 added defect! Jan-04 Apr-04 Jul-04 Sep-04 Dec-04 Source: SEMATECH 15

16 Cost/Pixel Trend w/tool Cost Ranges (Source: Normalized Cost/Pixel) Intel 03) Normalized Cost/Pixel Low Tool Cost High Tool Cost Cost/Pixel normalized to to 90nm Node Tool Cost Ranges based on on 2002 ISMT Exposure Tool Cost Survey Results 16

17 Transistor Trade-offs ε o ε s t ox Increase Cox =>Reduce t ox I DSat ~1 µc ox (W)(V DD V T ) 2 2 Lg S G Lg D W Reduce Lg Reduce V DD F Max = I DSat /V DD C ox Power= V DD2 C ox F Max 17

18 10 Gate Oxide Scaling ε o ε s 1 I DSat 1 µ (V DD V T ) ~ 2 W 2 Lg t ox 10.35um Gate Oxide Thickness (nm).25um Generation.18um.13um 90nm 1.2 nm Source: Intel 18

19 Gate Delay Trend F Max = I DSat /V DD C ox 100nm Source: Intel 19

20 Drive Current (ma/um) Transistor Performance ε o ε s 1 I DSat 1 µ (V DD V T ) ~ 2 W 2 Lg NMOS t ox Generation.25um.35um.18um.13um 90nm 10 Supply Voltage (V) 0.4 PMOS V Source: Intel 20

21 The Incredible Shrinking Silicon Technology in the 90s Salicide Gate Spacer Salicide Salicide Gate Spacer Salicide 0.35 µ µ 1997 Salicide Source: Intel Gate Spacer 0.18µ Salicide

22 New Transistor Trade-off I DSat ~1 µc ox (W)(V DD V T ) 2 2 Lg µ Reduce Lg Increase Cox Increase µ S G Lg D W 22

23 Strained Silicon Transistors Current Flow Normal electron flow Faster electron flow Normal Silicon Lattice Strained Silicon Lattice 23

24 The power challenge Intel Produces Power Efficient 90nm Transistors with Strained Silicon PMOS High Stress Film NMOS SiGe SiGe Compressive channel strain Tensile channel strain 30% drive current increase 10% drive current increase Innovate and integrate for cost effective production 24 Source: Intel

25 65nm Technology Highlights Intel 65 nm generation logic technology provides improved performance and reduced power: 1.2 nm transistor gate oxide 35 nm transistor gate length Enhanced strained silicon technology 8 layers of copper interconnect Low-k k dielectric This technology is being demonstrated on fully functional 70 Mbit SRAM chips with >0.5 billion transistors Intel s s 65 nm technology is on track for delivery in

26 The power challenge Gate oxide scaling has slowed µm µm Transistor performance Gate Oxide Thickness (nm) µm 0.18µm 1.2 nm 0.13µm 90nm nm 1 ε o ε s 1 I DSat 1 µ (V DD V T ) ~ 2 W 2 Lg t ox Mobility Slower scaling of one parameter can be compensated by speeding up another Source: Intel 26

27 65nm Process - Transistor 35nm Strained silicon enhanced for performance and power efficiency Source: Intel 27

28 65 nm Generation Interconnects Metal 8 layer is added for improved density and performance (1 more layer than 90 nm generation) Low-k carbon doped oxide dielectric reduces interconnect capacitance (improved from 90 nm generation) Interconnect capacitance is reduced by use of low-k dielectric and by ~0.7x line length scaling Lower capacitance improves interconnect performance and reduces chip power Power Saving Feature M8 M7 M6 M5 M4 M3 M2 M1 28

29 Defect Reduction Trend 130nm 130nm 90nm 65nm 200mm 300mm 300mm 300mm Defect Density (log scale) Two Years nm yield on same improvement rate with 2 years offset 29

30 Fully Functional Devices on Intel s 65nm Process Yonah Fully functional 70 Mbit SRAM ~110 mm 2 die size >0.5 billion transistors 30

31 Agenda Moore s s Law and scaling The power challenge Looking ahead 31

32 The power challenge Power Challenges Power challenges are neither new nor fundamental Will it be possible to remove the heat generated by 10 s of thousands of components? (Moore, 1965) Intel s s 1 st product 1969: bipolar b b RAM Intel takes a holistic approach From device/process power innovations Transistor optimization is a key to low-power To solutions at the platform level and beyond Intel continues to invest and innovate on Moore s Law R&D and capital Benefits to functions, performance/power, and cost 32

33 Moore s Law Silicon Technology Changes to Increase Power Efficiency Mid s: Bipolar, PMOS Mid s: NMOS Mid s: CMOS Mid s: CMOS, Voltage scaling Mid s: CMOS, Power efficient 33

34 90nm Strained Silicon Saves Transistor Leakage Current (na/um) Std Strain Std Strain +25% I ON +10% I ON x I OFF 0.20x I OFF 1 PMOS NMOS Transistor Drive Current (ma/um) 5X to 25X reduction in transistor leakage power Source: *Third Intel, party VLSI marks Technology and brands are Symposium the property of their 6/04respective owners

35 65 nm Generation Transistors 1.2 nm gate oxide, 35 nm gate length for improved performance 220 nm contacted gate pitch for improved density NiSi for low resistance cap on gates and source-drains Intel s s unique uniaxial strained silicon technology, first introduced on the 90 nm generation, is further enhanced on 65 nm transistors for improved performance At the 65 nm generation, strained silicon improves performance ~30% relative to non-strain Intel has developed a second generation of strained silicon technology while others are still struggling to develop their first generation 35

36 Improved Transistor Performance V PMOS NMOS I OFF 100 (na/um) nm nm I ON (ma/um) 65 nm transistors increase drive current 10-15% 15% with enhanced strain 36

37 Improved Transistor Performance V PMOS NMOS 100 I OFF (na/um) nm nm 2004 Power Saving Feature I ON (ma/um) 65 nm transistors can alternatively provide ~4x leakage reduction No other company has matched these performance-leakage capabilities 37

38 The power challenge Strained Silicon Intel 90nm strain silicon has been in volume production since 2003 Observed leakage N-Channel -> > 5X Reduction P-Channel-> > >5X Reduction Intel 65nm technology has been successfully demonstrated in 2004 using 2 nd Generation Strained Silicon Observed a further leakage from 90nm process N-Channel -> > 4X Reduction P-Channel -> > >4X Reduction 38

39 Reduced Gate Capacitance at 65nm Gate oxide thickness is held constant at 1.2 nm to avoid increased gate leakage Gate capacitance (C GATE ) reduced ~20% due to smaller gate length (35 nm) Source Gate C GATE Drain Lower gate capacitance reduces chip active power Combination of higher drive current and lower gate capacitance provides ~1.4x increase in switching frequency Substrate Power Saving Feature 39

40 The power challenge Lower Junction Capacitance Speeds up Circuits C WIRE 1 C WIRE (1- Cj/C total) Gate Gate C GATE C GATE Source Drain Source Drain C JUNCT Substrate Oxide Substrate SOI reduces junction capacitance (under 5% of total), but not gate or wire capacitance 40

41 Bulk CMOS vs. PDSOI For illustration only Planar CMOS Gate Partially Depleted SOI Gate SiO 2 SiO 2 SiO 2 SiO 2 Silicon Substrate Silicon Buried Substrate Oxide Silicon Substrate 41

42 The power challenge Intel Already Has the Lowest Junction Capacitance (180nm data) Junction 1.00 Capacitance 0.80 (ff/µm 2 ) 0.60 N+/PWell P+/Nwell Wang, EDL Oct.'00 Mehrotra IEDM '99 Imai, IEDM '99 Yoshimura, VLSI '00 Diaz, VLSI '00 Yeap, VLSI '00 Intel Intel Bias (V) Intel achieves the industry s lowest junction capacitance without SOI, thereby avoiding the cost of SOI S. Tyagi, IEDM

43 The power challenge Net Impact of SOI Goes Down with Each Generation All 3 elements of SOI performance diminish with scaling - Gain for 90nm node: 3-10% depending on history guardband 0.18um 130nm 90nm F.O.=1 Inverter 16% 13% 11% F.O.=4 Inverter 8% 7% 6% 3-Input NAND 20% 17% 14% Average 15% 12% 10% History Guardband -5% -6% -7% NET 10% 6% 3% Analysis ignores interconnect load, which reduces SOI gain further K. Mistry, VLSI

44 Intel s s bulk CMOS has extremely low Cj 1 (1- Cj/C total) Example for Illustration only Low Cj =~ 0.1 x C total Gross performance gain = 1/(1-0.1) = 11% Net gain is low Bulk substrate cost much less If Cj = ~0.25 x C total Then, gross performance gain = 1/(1 0.25) = 33% Net gain is high High Cj is indicative of an under optimized bulk CMOS process 44

45 Has SOI solved the leakage problem? No SOI eliminated junction leakage Junction leakage is < 5% of total leakage in Intel process Ioff of Intel Strained Silicon is >10x lower than any reported data, Including SOI R GATE R GATE R JUNCT R SD Oxide R SD Si Substrate Si Substrate BULK SOI SOI reduces junction capacitance, but not gate or wire capacitance 45

46 The power challenge Summary of Strained Silicon vs. SOI Intel 90nm strain silicon has been in volume production since 2003 Partially depleted (PD)-SOI has no place on Intel roadmap: Intel has thoroughly evaluated costs/benefits Is saving millions per year on substrate alone by avoiding SOI Cost adder is 15% or more Performance benefit is less than 5% at 90nm Intel demonstrated transistors with world-leading leading performance/leakage characteristics: Low-junction junction-capacitance capacitance bulk CMOS at 130nm Uniaxial strained silicon at 90nm and beyond Fully depleted (FD)-SOI (e.g. Tri-gate) has been under evaluation for future: Final decision depends on costs/benefits 46

47 Sleep Transistors Reduce Leakage Power V DD 70 Mbit SRAM IR photos SRAM Cache Sub-Block NMOS Sleep Transistor V SS Normal SRAM sub-block block leakage Sleep transistors shut off leakage in inactive sub-blocks blocks >3x SRAM leakage reduction with use of sleep transistors Power Saving Feature 47

48 The power challenge Silicon Scaling Continues to Improve Density, Performance, Power, Cost Mobile CPUs Pentium M processor Frequency Transistors Die size L2 cache Thermal design power 130 nm (Banias) 1.7 GHz 77 million 83 mm 2 1 MB 24.5 W 90 nm (Dothan) 2.1 GHz 140 million 87 mm 2 2 MB 21 W Source: Intel 48

49 The power challenge Sleep Transistors Reduce ALU Leakage V cc external PMOS underdrive V cc Sleep transistors PMOS Sleep Body Bias ALU Body Bias PMOS overdrive V ss Virtual V cc Dynamic ALU 32 Scan Scan FIFO Sleep ALU Scan out Control Sleep transistor and body bias control ALU core NMOS overdrive V cc Virtual V ss Scan capture control Body bias 37X leakage reduction demonstrated on test chip NMOS underdrive V ss 3-bit A/D V ss external 49 Source: ISSCC 2003, Paper 6.1

50 The power challenge Advances in Power Efficient Design Power (W) Cache Switch Cache Igate Cache Ioff Core Switch Core Igate Core Ioff From ISSCC 2005 Paper 10.1 The Implementation of a 2-core 2 Multi-Threaded Itanium TM Family Processor Using prior design techniques IO bias DCAP lkg With new power reduction techniques 50

51 Business Critical Features 1MB L2I mm 2-Way Multi- Threading 1.72 Billion transistors Dual Cores Foxton Power Controller 21.5 mm Soft Error Detection and Correction 2 X 12MB L3 Caches with Pellston 51

52 The power challenge Silicon Scaling Continues to Improve Density, Performance, Power, Cost Server CPUs 130 nm 90 nm Madison Montecito Cores/Threads 1/1 2/4 Transistors Billion L3 Cache 6 24 MByte Frequency 1.5 >1.7 GHz Relative Performance 1 >1.5x Thermal Design Power 130 ~100 Watt Source: Intel 52

53 The power challenge Dual Core Cache Cache Core Core Core Voltage = 1 Freq = 1 Power = 1 Perf = 1 Voltage = -15% Freq = -15% Power = 1 Perf = ~1.8 Figures are for illustrative purposes only; actual results may vary 53

54 The power challenge Multi-Core Cache Large Core Power 4 Performance Small 1 1 Core Power = 1/4 Performance = 1/2 1 1 C1 C3 Cache C2 C Multi-Core: Power efficient Better power and thermal management 54

55 The power challenge Performance and Power Efficiency Increase with Parallel Architecture 100 Relative processor performance* (constant power 10 envelope) SINGLE-CORE DUAL/MULTI-CORE 10X 1 3X FORECAST *Average of SPECInt2000 and SPECFP2000 rates for Intel desktop processors vs initial Intel Pentium 4 Processor 55 Source: Intel

56 Agenda Moore s s Law and scaling The power challenge Looking ahead 56

57 Future High-k k Dielectric Will Reduce Gate Leakage Gate 1.2nm SiO 2 Silicon substrate Gate capacitance Gate dielectric leakage High-k k vs. SiO 2 60% greater > 100x reduction Gate 3.0nm High-k Silicon substrate Benefit For Future Implementation Faster transistors Lower power 57

58 Gate Dielectric Scaling (High-K) um Gate Dielectric Thickness (nm) Generation.25um.18um K=3XK D K=5XK D.13um 90nm 1.2 nm Thinner equivalent gate oxide increases transistor performance 58

59 Continuation of Moore s s Law Intel Intel found a solution for for High-k and and metal gate gate Process Name P856 P858 Px60 P1262 P1264 P1266 P1268 P1270 1st Production Process Generation 0.25µm 0.18µm 0.13µm 90 nm 65 nm 45 nm 32 nm 22 nm Wafer Size (mm) / Inter-connect Al Al Cu Cu Cu Cu Cu? Channel Si Si Si Strained Si Strained Si Strained Si Strained Si Strained Si Gate dielectric SiO 2 SiO 2 SiO 2 SiO 2 SiO 2 High-k High-k High-k Gate electrode Poly- silicon Poly- silicon Poly- silicon Poly- silicon Poly- silicon Metal Metal Metal Potential candidate for introduction Subject to change Source: 59 Intel

60 Looking ahead Nanotechnology Hallmarks Structures measured in nanometers Less than 0.1-micron (100nm) New processes, materials, device structures Incrementally changing silicon technology base Materials manipulated on atomic scale In one or more dimensions Increasing use of self-assembly Using chemical properties to form structures Nanotechnology innovations will extend silicon technology and Moore s s Law 60

61 Surrounding the Semiconductor Source Metal Gate Insulator Drain Source Drain Drain Gate Source Drain Source Gate BOX Si fin - Body! FinFET Tri-Gate 61

62 Tri-gate Transistor works in Three Dimensions Planar CMOS Gate Tri-Gate Gate 1 SiO 2 SiO 2 Gate 2 Gate 3 Silicon Substrate Buried Oxide 62

63 New Device Architecture Tri-gate L g Si T Si (Planar) Planar fully depleted SOI Isolation T Si L g W Si L g W Si Double-gate (e.g. FINFET) (Non-Planar) T Si Most Manufacturable Tri-gate (Non-Planar) 63

64 Tri-Gate Transistor: A A template for the future GATE DRAIN GATE SOURCE DRAIN SOURCE Source: Intel CHANNEL- Si, nanotubes, nanowires Technical details presented at: ISSDM Conference, Japan, Sept 17,

65 Nano-Device Structure Evolution Conventional Planar Transistor Tri-gate Transistor Gate SiO2 SiO2 Fully-Surround Gate Transistor Gate Improved Electrostatics Best Electrostatics and Scalability Improving electrostatics optimizes power consumption *Third party marks and brands are the and property of performance their respective owners 65

66 Semiconductor Nanowires 5nm Si Nanowire Chemically synthesized silicon nanowires with diameters <20nm (not defined by lithography). 2.0 nm High-K Metal Gate Si Nanowire Source: Intel 66

67 Carbon Nanotube Tutorial Metal R r Semiconductors Semiconductor Rolled-up graphene sheet(s) Roll-up vector determines electronic properties of tubes metallic semiconducting Dimensions: 1-25nm depending on how they are form. 67

68 Carbon Nanotube Transistor Drain Carbon Nanotube - D = 1.4 nm Source L g = 75 nm Gate Source: Intel Chemically synthesized semiconducting nanotubes with diameter=2nm form the transistor channel. 68

69 Energy-delay product for PMOS CNT shows promise! 69

70 Looking ahead Compound Semiconductor (lll( lll-v) Transistors Source Gate Source: Intel Drain Source Multi epitaxial layers Research transistor based on multi-epitaxial layer structure in compound semiconductors. 70

71 Looking ahead CMOS to continue for years or more; Moore s s Law could be extended indefinitely via new architectures, heterogeneous integration, 3D Transistor Speed Power Consumption 0.2um InSb 0.2um NMOS (standard transistor) 0.2um InSb 0.2um NMOS (standard transistor) III/V is a 2015 Transistor option 3x faster or 10x lower power Integration with silicon key 71

72 Energy-delay product for NMOS III-V transistors show promise! 72

73 Transistor Scaling & Roadmap 90nm Node nm Node P nm Node 2005 P nm Length (Production) 30nm 30nm Length (Development) Uniaxial Strain SiGe S/D 20nm Length (Development) Source Drain Source High-K/ Metal-Gate 32nm Node P nm 25 nm 15nm Length (Research) Source Gate Drain 22nm Node P L G = 10nm 10nm Length (Research) Silicon Body S G D C-nanotube Prototype (Research) Non-planar Tri-Gate Architecture III-V 5 nm III-V Device Prototype (Research) Nanowire Prototype (Research) 73 5nm

74 Moore s Law Moore s s Law Today Moore s s Law = Doubling of components at fixed intervals while reducing production cost/component Moore's Law is alive and well CMOS has been an important enabler of Moore s s Law Moore's Law may go on indefinitely, and extend beyond traditional CMOS End of CMOS Scaling End of Moore s s Law 74

75 Looking ahead Transistors/Die Moore s s Law Will Outlive CMOS 10µm 13 Bipolar PMOS NMOS CMOS Voltage Scaling Data (Moore) Memory Microprocessor Kilo Xtor 1µm 100nm 10nm Mega Xtor Pwr Eff Scaling Giga Xtor New Nano- structures Beyond CMOS? Spin based? Molecular? Other? Tera Xtor 75

76 Expanding Moore s s Law Sensors EXPANDING EXPANDING Optical Biological 25 nm 15nm Nano Fluidics 50nm Prototype (IEDM2002) 15nm Prototype (IEDM2001) 10nm Prototype (DRC 2003) Mechanical Wireless Silicon manufacturing infrastructure will enable innovation 76

77 Heterogeneous Integration of Alternative Technologies Courtesy of European Nanotechnology Roadmap 77

78 Summary Scaling (Geometrical->Equivalent >Equivalent->Innovative-> > Power efficient_> New nanostructures-> > Beyond CMOS) will continue, facilitated by the availability of more knobs (e.g., high mobility, high-k, low-k, thin body, multi-gates, CNT, new devices, etc) well into the next decade and beyond Intel is taking a holistic approach to reducing power Silicon level Architectural/micro-architectural: architectural: parallelism everywhere Platform, software Intel continues to observe the principles of Moore s Law Thoroughly evaluating technology options Ensuring optimum performance/power benefits and costs Delivering best value on our products/platforms Moore s s Law will continue beyond CMOS 78

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