Chapter 7 Introduction to 3D Integration Technology using TSV

Transcription

1 Chapter 7 Introduction to 3D Integration Technology using TSV Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

2 Outline Why 3D Integration An Exemplary TSV Process Flow Stacking Strategies Concept of 3D IC Design Summary Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

3 IC Technology Evolution Chip Single-chip package Printed wiring board(pcb) 3D-SIP Chemical & Bio Sensors Other Sensors, Imagers Nano Device MEMS RF ADC DAC Memory Stack 3D-IC Processor Energy/Power Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU

4 Why 3D Integration Integrating more and more transistors in a single chip to support more and more powerful functionality is a trend Using 2D integration technology to implement such complex chips is more and more expensive and difficult Some alternative technologies attempting to cope with the bottlenecks of 2D integration technology have been proposed 3D integration technology using through silicon via (TSV) has been acknowledged as one of the future chip design technologies Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

5 3D Integration Technology Using TSV 3D integration technology using TSV Multiple dies are stacked and TSV is used for the inter-die interconnection Die 1 Die 2 Die 3 The fabrication flow of a 3D IC Die/wafer preparation Die/wafer assembly TSV Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5

6 What is TSV Through Silicon Via (TSV): A via that goes through the silicon substrate Used for dies stacking Top Bump Al wiring TSV Wiring layer Diameter CMOS 50 um or less Via made by laser SiO 2 insulator Top Bump Typical TSV technologies Via-first, via-middle, and via-last technologies Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

7 Via-First TSV Technology Via-First TSV (1) Before CMOS (2) After CMOS & BEOL Source: Yole, Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7

8 Via-Last TSV Technology Via-Last TSV (1) After BEOL & before bonding (2) After bonding Source: Yole, Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8

9 An Exemplary Via-Last Process Flow (1/6) Step 1: A wafer with CMOS circuits MOSFET MOSFET Ref :ITRI Substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9

10 An Exemplary Via-Last Process Flow (2/6) Step 2: via etching Via machining (by etching or laser dilling) MOSFET MOSFET Ref :ITRI Substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10

11 An Exemplary Via-Last Process Flow (3/6) Step 3: via filling Via filling MOSFET MOSFET Ref :ITRI Substrate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11

12 An Exemplary Via-Last Process Flow (4/6) Step 4: wafer thinning 50 ~ 100 μm Wafer thinning Ref :ITRI Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12

13 An Exemplary Via-Last Process Flow (5/6) Step 5: micro bump forming Micro Bump Ref :ITRI Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13

14 An Exemplary Via-Last Process Flow (6/6) Step 6: stacking TSV Micro (μ) Bump ABF(Ajinomoto Built-in Film) Ref :ITRI Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14

15 An Exemplary 3D IC using Via-Last TSV Bonding Adhesive P-Substrate Bonding Adhesive 3 rd Chip N+ P+ P+ N+ N+ P+ N+ P+ N+ N+ P+ N+ N Well N Well N Well P-Substrate TSV 2 nd Chip N+ P+ P+ N+ N+ P+ N+ P+ N Well N Well N+ N+ P+ N+ N Well P-Substrate TSV 1 st Chip Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15

16 3-Tier 3D IC Cross-Section Source: E. G. Friedman, University of Rochester. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16

17 Die/Wafer Assembly Bonding technologies for 3D ICs Wafer-to-wafer (W2W), Die-to-Wafer (D2W), and Die-to-Die (D2D) Comparison of different bonding technologies D2D D2W W2W Yield Flexibility Production Throughput High High Low High Good Good Low Poor High Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

18 Stacking Strategies μ Bump μ Bump μ Bump Die2 TSV D2D Vias Metal Die1 Active Si Bulk Si face-to-face back-to-back face-to-back Lewis, D.L. et al, A ScanIsland Based Design Enabling Prebond Testability in DieStacked Microprocessors, in proc. IEEE International Test Conference (ITC), 2007, pp. 1-8 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18

19 Fabrication Steps for Face-to-Face Stacking Die2 4 5 Die2 Die2 Metal Metal Metal Metal Metal Active Si Active Si Active Si Active Si Active Si Bulk Si Bulk Si Bulk Si Die1 Die2 Die1 Die2 Die1 Bulk Si Die1 Bulk Si Die1 Loh, Gabriel H. et al, Processor Design in 3D Die-Stacking Technologies, in IEEE Micro, vol.27, issue 3, pp , 2007 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

20 Fabrication Steps for Face-to-Back Stacking Die2 Die2 Handle wafer Metal Metal Metal Metal Metal Active Si Active Si Active Si Active Si Active Si Bulk Si Die1 Die2 Bulk Si Die1 Die2 Bulk Si Die1 Die2 Bulk Si Die1 Bulk Si Die1 Loh, Gabriel H. et al, Processor Design in 3D Die-Stacking Technologies, in IEEE Micro, vol.27, issue 3, pp , 2007 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20

21 Electrical Characteristics of TSV Capacitance of TSV Top Bump Al wiring TSV Wiring layer TSV Length Diameter CMOS Dielectric Thickness TSV Dia [um] TSV Diel Thk [nm] TSV Length [um] Cap [ff] Source: Proceedings of IEEE, pp. 101, Jan Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

22 RC Characteristics of TSV Die2 1 FO4 = 22 ps (BSIM 70nm) Die1 D2D via M9 ~ 0.35*RC viastack via9 225 ps > 11 FO4 M2 via2 RC viastack 4x minimum size 1-mm top-level metal M1 via1 F2F D2D via 8 ps ~ 1/3*FO4 MOSFET Loh, Gabriel H. et al, Processor Design in 3D Die-Stacking Technologies, in IEEE Micro, vol.27, issue 3, pp , 2007 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22

23 Benefits of 3D Integration Benefits of 3D integration over 2D integration High functionality High performance Small form factor Low energy Source: Proceedings of IEEE, Jan Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23

24 High Functionality Heterogeneous integration Combine disparate technologies DRAM, flash, RF, etc. Combine different technology nodes E.g., 65nm technology and 45nm technology Chemical & Bio Sensors Other Sensors, Imagers Nano Device MEMS RF ADC DAC Memory Stack Processor Energy/Power Source: Proceedings of IEEE, Jan Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24

25 High Performance 3D integration technology can reduce the length of the long interconnections using TSV For example, x x x x y B 1 2 B 1 2 z y A 3 4 y A 3 4 L 2D =x+2y L 3D =x+y+z Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25

26 High Bandwidth 3D IC allows much more IO resources than 2D IC For example, Stacking of processor and memory Memory Memory CPU CPU Bandwidth is limited by IOs Many TSVs are allowed for high bandwidth transportation Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26

27 Low Energy Energy SOB SIP 3D-IC Technology Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

28 3D IC Design Approaches L2 CPU L2 L2 Multiple Cores rs rf rob Idq bpred D$ IF tlb I$ alu stq dec L2 Entire Core Function Unit Block (FUB) VDD X gnd Y Logic gates (FUB splitting) Transistors (circuit) Level Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28

29 2D RAM Bitlines Wordlines Block 0 Block 1 Block 2 Block 3 Address input Data output Mux & SA Mux & SA Mux & SA Mux & SA WL Pre-Dec Mux & SA Mux & SA Mux & SA Mux & SA Block 4 Block 4 Block 4 Block WLs RAM Subarray 256 BLs Y.-F. Tsai et al, Design Space Exploration for 3-D Cache, IEEE Transactions on Very Large Scale Integration (TVLSI), vol.16, issue 4, pp , 2008 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29

30 3D Wordline-Partitioned RAM 128 WLs Block 0-2 Block 1-2 Block 2-2 Block 3-1 SA 0-2 SA 1-2 WL Pre-Dec SA 2-2 SA 3-1 Block 4-2 Block 5-2 Block 5-2 Block 6-2 SA 4-2 SA 5-2 Block 6-2 Block 7-2 SA 6-2 SA 7-1 Block 7-1 Block 0-2 Block 1-2 Block 2-2 Block 3-2 Address input Data output SA 0-2 SA 4-2 SA 1-2 WL Pre-Dec SA 5-2 SA 2-2 SA 6-2 SA 3-2 SA 7-2 Block BLs Y.-F. Tsai et al, Design Space Exploration for 3-D Cache, IEEE Transactions on Very Large Scale Integration (TVLSI), vol.16, issue 4, pp , 2008 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30

31 3D Bitline-Partitioned RAM Block 0-2 Block 1-2 Block 2-2 Block 3-2 Address input Data output Mux & SA WL Dec Mux & SA Block 4-2 Block 0-2 Mux & SA Mux & SA Block 4-1 Mux & SA WL Dec Mux & SA Block 5-2 Block 1-2 Block 2-2 WL Pre-Dec Mux & Mux & SA Mux & SA SA WL Pre-Dec Mux & Block 6-2Mux & SA SA Block 5-1 Mux & SA WL Dec Block 6-1 Mux & SA Block 3-1 WL Dec Mux & SA Mux & SA Block 7-2 Mux & SA Block WLs 256 BLs Y.-F. Tsai et al, Design Space Exploration for 3-D Cache, IEEE Transactions on Very Large Scale Integration (TVLSI), vol.16, issue 4, pp , 2008 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

32 Design Example: 3D RAM Source: G. H. Loh, ISCA 2008 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32

33 Design Example Source: ASP-DAC Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33

34 Road Map of 3D Integration with TSVs Source: Proceedings of IEEE, Jan Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34

35 Summary 3D integration technology using TSV is one of future IC design technologies It can offer many advantages over the 2D integration technology However, there are some challenges should be overcome before volume-production of TSVbased 3D IC becomes possible Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35