Nanoscale III-V Electronics: from Quantum-Well Planar MOSFETs to Vertical Nanowire MOSFETs

Transcription

1 Nanoscale III-V Electronics: from Quantum-Well Planar MOSFETs to Vertical Nanowire MOSFETs J. A. del Alamo Microsystems Technology Laboratories, MIT Purdue University, West Lafayette, IN; September 29, 2015 Acknowledgements: D. Antoniadis, J. Lin, W. Lu, A. Vardi, X. Zhao Sponsors: DTRA, Lam Research, Northrop Grumman, NSF, Samsung Labs at MIT: MTL, EBL

2 Contents 1. Motivation: Moore s Law and MOSFET scaling 2. Planar InGaAs MOSFETs 3. InGaAs FinFETs 4. Vertical nanowire InGaAs MOSFETs 5. Conclusions 2

3 1. Moore s Law at 50: the end in sight? 3

4 Moore s Law Moore s Law = exponential increase in transistor density Intel microprocessors 4

5 What if Moore s Law had stopped in 1990? GPS handheld device circa 1990 Cell phone circa

6 What if Moore s Law had stopped in 1980? Laptop computer circa

7 What if Moore s Law had stopped in 1970? TV set, circa

8 What if Moore s Law had never happened? Insulin pump circa 1960 Personal calculator circa

9 Moore s Law How far can Si support Moore s Law?? 9

10 Transistor scaling Voltage scaling Performance suffers Transistor current density (planar MOSFETs): Transistor performance saturated in recent years 10

11 Moore s Law: it s all about MOSFET scaling 1. New device structures: Enhanced gate control improved scalability 11

12 Moore s Law: it s all about MOSFET scaling 2. New materials: Si Strained Si SiGe InGaAs Si Strained Si SiGe Ge InGaSb Future CMOS might involve two different channel materials with two different relaxed lattice constants! del Alamo, Nature 2011 (updated) 12

13 Electron velocity: InGaAs vs. Si Measurements of electron injection velocity in HEMTs: del Alamo, Nature 2011 v inj (InGaAs) increases with InAs fraction in channel v inj (InGaAs) > 2v inj (Si) at less than half V DD ~100% ballistic transport at L g ~30 nm 13

14 III-V electronics in your pocket! 14

15 del Alamo s group at MIT: Current and future activities N-type InGaAs MOSFETs: Jianqiang Lin Alon Vardi Xin Zhao New students: Xiaowei Cai Dongsung Choi P-type InGaSb MOSFETs: Wenjie Lu future 15

16 2. Self-aligned Planar InGaAs MOSFETs dry-etched recess selective MOCVD W Mo Lin, IEDM 2012, 2013, 2014 Lee, EDL 2014; Huang, IEDM 2014 implanted Si + selective epi reacted NiInAs Sun, IEDM 2013, 2014 Chang, IEDM

17 Self-aligned Planar InGaAs MIT W Mo Jerome Lin Lin, IEDM 2012, 2013, 2014 Recess-gate process: CMOS-compatible Refractory ohmic contacts (W/Mo) Extensive use of RIE 17

18 Fabrication process Mo/W ohmic contact + SiO 2 hardmask SF 6, CF 4 anisotropic RIE Resist CF 4 :O 2 isotropic RIE SiO 2 W/Mo n + InGaAs/InP InGaAs/InAs InAlAs δ-si InP Waldron, IEDM 2007 Cl 2 :N 2 anisotropic RIE Digital etch Finished device O 2 plasma H 2 SO 4 Pad Mo HfO 2 Lin, EDL 2014 Ohmic contact first, gate last Precise control of vertical (~1 nm), lateral (~5 nm) dimensions MOS interface exposed late in process 18

19 L g =20 nm InGaAs MOSFET SiO 2 W Mo n + cap Channel Buffer 20 nm Ti/Au pad Gate: Mo Spacer: Oxide Contact: Mo Mo/HfO 2 20 nm 15 nm 1.0 L g =20 nm V gs -V t = 0.5 V 0.8 R on =224 Ω.µm 0.4 V InAs V ds (V) I d (ma/µm) L g = 20 nm, L access = 15 nm MOSFET most compact III-V MOSFET made at the time Lin, IEDM

20 Highest performance InGaAs MOSFET Channel: In 0.7 Ga 0.3 As/InAs/In 0.7 Ga 0.3 As Gate oxide: HfO 2 (2.5 nm, EOT~ 0.5 nm) I d (ma/µm) V gs = -0.3 to 0.4 V in 0.1 V step L g = 80 nm R on =190 Ω.µm V ds (V) L g =80 nm, t c =9 nm g m (ms/µm) gm,max = 3.1 ms/µm L g = 80 nm V ds = 0.5 V V gs (V) Record g m,max = 3.1 ms/µm at V ds = 0.5 V R on = 190 Ω.µm Lin, IEDM

21 Excess OFF-state current Transistor fails to turn off: I d (A/µm) 10-5 L g =500 nm V ds V ds =0.3~0.7 V step=50 mv V gs (V) OFF-state current enhanced with V ds Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL) Lin, IEDM

22 Excess OFF-state current I d (A/µm) T=200 K V ds =0.7 V L g =80 nm 120 nm 280 nm 500 nm V gs -V t (V) Lin, EDL 2014 Lin, TED 2015 L g OFF-state current additional bipolar gain effect due to floating body I d (A/µm) I d (A/µm) 10-5 L g =500 nm w/ W/ BTBT+BJT w/o W/O BTBT+BJT L g =500 nm V ds V ds =0.3~0.7 V step=50 mv V gs (V) Simulations V ds =0.3~0.7 V step=50 mv V gs (V) 22

23 Impact of channel thickness scaling S min (mv/dec) t c =12 nm t c 3 nm V ds =0.5 V V ds =0.5 V L g (µm) g m,max (ms/µm) nm 11 nm 7 nm 12 nm 4 nm 3 nm Lin, IEDM 2014 Lin, TED 2015 t c =9 nm V ds =0.5 V L g (µm) t c S but also g m,max Even at t c =3 nm, L g,min ~40 nm planar MOSFET at limit of scaling 23

24 Benchmarking: g m in MOSFETs vs. HEMTs g m of InGaAs MOSFETs vs. HEMTs (any V DD, any L g ): Latest: 3.7 ms/µm! MIT MOSFETs del Alamo, ESSDERC 2013 (updated) Very rapid recent progress in MOSFET g m Best MOSFETs now surpass best HEMTs No sign of stalling more progress ahead! 24

25 3. InGaAs FinFETs and Trigate MOSFETs 60 nm dry-etched fins Kim, IEDM 2013 Epi-grown fin inside trench Si Waldron, VLSI Tech

26 InGaAs MIT Alon Vardi Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE digital etch Zhao, EDL 2014; Vardi, DRC

27 Interface-state study on sidewalls of InGaAs FinFET Long-channel MOSFET characteristics (W f =12~37 nm): I D [µa/µm] 20 Wf =12 nm L g =5 μm V GS =0.5 V V GS =0 V V DS [V] At sidewall: D it,min ~ 3x10 12 ev -1.cm -2 Vardi, DRC

28 Sub-10 nm fin width InGaAs FinFETs InGaAs doped channel: 50 nm thick N D ~10 18 cm -3 Oxide: Al 2 O 3 /HfO 2 (EOT~3 nm) W f =7 nm, L g =3 µm MOSFET Fin width: 5 ~ 35 nm Fin height: 130 nm 100 fins Vardi, IEDM

29 4. Lateral vs. Vertical Nanowire MOSFETs 5 nm node Yakimets, TED 2015 Bao, ESSDERC % area reduction in 6T-SRAM 19% area reduction in 32 bit multiplier Nanowire MOSFET: ultimate scalable transistor Vertical NW: uncouples footprint scaling from L g and L c scaling power, performance and area gains wrt. Lateral NW 29

30 InGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Vapor-Solid-Liquid (VLS) Technique Selective-Area Epitaxy Riel, MRS Bull 2014 Björk, JCG

31 InGaAs VNW-MOSFETs by bottom-up techniques Many device demonstrations: Tanaka, APEX 2010 Tomioka, Nature 2012 Persson, DRC

32 InGaAs VNW-MOSFETs fabricated via top-down MIT Xin Zhao Starting heterostructure: n + InGaAs, 70 nm i InGaAs, 80 nm n + InGaAs, 300 nm n + : Si doping Top-down approach: flexible and manufacturable Zhao, IEDM

33 Key enabling technology I: RIE by BCl 3 /SiCl 4 /Ar chemistry 28 nm 240 nm Sub-30 nm resolution Aspect ratio > 8 Smooth sidewall and surface Substrate temperature critical during RIE Zhao, EDL

34 Key enabling technology II: digital etch Self-limiting O 2 plasma oxidation + H 2 SO 4 oxide removal Rate (nm/cycle) Experiment Model Oxidation time (s) before after 5 cycles Planar etching rate: ~1 nm/cycle Shrinks NW diameter by 2 nm per cycle Unchanged shape Reduced roughness Lin, EDL 2014 Zhao, EDL

35 Optimized RIE + Digital Etch 15 nm 240 nm Zhao, EDL 2014 Sub-20 nm resolution Aspect ratio = 16, vertical sidewall Smooth sidewall and surface 35

36 Tomioka, Nature 2012 Persson, DRC 2012 Process flow 36

37 I d (µa/µm) NW-MOSFET I-V characteristics D=30 nm V gs =-0.6 V to 0.8 V in 0.1 V step R on =759 Ω.µm (at V gs =1 V) V ds (V) I d (µa/µm) g m, pk (V ds =0.5 V) =280 µs/µm V ds =0.5 V V gs (V) g m (µs/µm) Single nanowire MOSFET: L ch = 80 nm 4.5 nm Al 2 O 3 (EOT = 2.2 nm) At V DS =0.5 V: g m,pk =280 μs/μm R on =759 Ω.μm Zhao, IEDM

38 S (mv/dec) g m (µs/µm) Impact of nanowire diameter V ds =0.5 V V ds =0.05 V Diameter (nm) V ds =0.5 V Diameter (nm) DIBL (mv/v) R on (Ω.µm) V gs =1 V Diameter (nm) Diameter (nm) D S, DIBL, g m, R on Error bars indicate distribution of ~10 devices 38

39 Impact of digital etch Single nanowire MOSFET: D= 30 nm (final diameter) Zhao, EDL 2014 Digital etch S, g m Better sidewall interface 39

40 Persson, EDL 2012 g m,pk (µs/µm) Benchmarking Tanaka, APEX 10 Tomioka, IEDM 11 Tomioka, Nature 12 Persson, DRC 12 Persson, EDL 10 This work (Top down) This work V ds =0.5 V S(mV/dec) Bottom up Persson, DRC 2012 Tomioka, Nature 2012 Tanaka, APEX 2010 Trade-off: D S but also g m Top-down approach as good as bottom-up approach 40

41 InGaAs VNW MOSFET Concerns (a short list ) Relatively poor subthreshold behavior S [mv/dec] small V DS DIBL [mv/v] Auth, EDL 1997 L g /λ eff L g /λ eff Electrostatic characteristic length for GAA NW 41

42 InGaAs VNW MOSFET Concerns (a short list ) Excess I off due to BTBT + Floating BJT Quantization enhances bandgap Vertical bandgap engineering InAs NWs Wang, ACSNano

43 InGaAs VNW MOSFET Concerns (a short list ) InGaAs low DOS limits current Increase in injection velocity with carrier density more than compensates for this D=5 nm (?) NW MOSFET Yu, TED

44 InGaAs VNW MOSFET Concerns (a short list ) V T sensitivity to nanowire diameter very tight manufacturing tolerance W f =8 nm Trigate MOSFETs Gray: nanowire array Individual nanowires Agrawal, TED 2013 Teherani, PhD MIT,

45 InGaAs VNW MOSFET Concerns (a short list ) Asymmetric device behavior: D down D up more restrictive circuit wiring I d (µa/µm) V gs = -0.6 to 0.6 V in 0.2 V step D = 40 nm, L g = 80 nm Drain at bottom Drain on top V ds (V) 45

46 InGaAs VNW MOSFET Concerns (a short list ) Sensitivity to few defects 200 V gs =-0.6 V to 0.8 V in 0.1 V step R on =759 Ω.µm (at V gs =1 V) I d (µa/µm) V ds (V) D=7 nm, L g =14 nm (5 nm design rules) S g =540 nm 2 D it =2x10 11 cm -2.eV -1 N it ~1 ev -1 46

47 InGaAs VNW MOSFET Concerns (a short list ) Top contact resistance Difficult to introduce mechanical stress Self-heating 47

48 Conclusions 1. Great recent progress on planar, fin and nanowire III-V MOSFETs 2. Vertical Nanowire III-V MOSFET: superior scalability and power/performance characteristics 3. Vertical Nanowire n- and p-type III-V MOSFET: plausible path for co-integration on Si 4. Many demonstrations of InGaAs VNW MOSFETs by bottom-up and top-down approaches 5. Many issues to work out: sub-10 nm diameter nanowire fabrication, self-aligned contacts, device asymmetry, Introduction of mechanical stress, V T control, device variability, BTBT and parasitic HBT gain, trapping, self-heating, reliability, co-integration with p-type VNW on Si, 48

49 A lot of work ahead but exciting future for III-V electronics 49