Towards Sub-10 nm Diameter InGaAs Vertical nanowire MOSFETs and TFETs

Transcription

1 Towards Sub-10 nm Diameter InGaAs Vertical nanowire MOSFETs and TFETs J. A. del Alamo, X. Zhao, W. Lu, and A. Vardi Microsystems Technology Laboratories Massachusetts Institute of Technology 5 th Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop Berkeley, CA, October 19-20, 2017 Acknowledgements: Students and collaborators: D. Antoniadis, E. Fitzgerald, E. Yablonovitch Sponsors: DTRA, KIST, Lam Research, Samsung, SRC Labs at MIT: MTL, EBL

2 Vertical Nanowire MOSFETs: the ultimate scalable transistor 2

3 Vertical nanowire MOSFET: ultimate scalable transistor L L c spacer L g Vertical NW MOSFET: uncouples footprint scaling from L g, L spacer, and L c scaling 3

4 InGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Riel, MRS Bull 2014 Vapor-Solid-Liquid (VLS) Technique Selective-Area Epitaxy (SAE) Riel, IEDM

5 InGaAs VNW-MOSFETs by top-down MIT Starting heterostructure: n + InGaAs, 70 nm i InGaAs, 80 nm n + InGaAs, 300 nm n + : cm -3 Si doping Top-down approach: flexible and manufacturable 5

6 InGaAs Vertical MIT Key enabling technologies: RIE = BCl 3 /SiCl 4 /Ar chemistry Digital Etch (DE) = self-limiting O 2 plasma oxidation + H 2 SO 4 or HCl oxide removal Radial etch rate=1 nm/cycle Sub-20 nm NW diameter Aspect ratio > 10 Smooth sidewalls RIE + 5 cycles DE Zhao, IEDM 2013 Zhao, EDL 2014 Zhao, IEDM

7 III-V VNW MOSFET/TFET process flow 7

8 NW-MOSFET I-V characteristics: D=40 nm I s (µa/µm) 300 V gs =-0.2 V to 0.7 V in 0.1 V step V ds (V) g m (µs/µm) V ds =0.5 V 10-4 V d = 0.5 V g m,pk =720 μs/μm Zhao, CSW V gs (V) Single nanowire MOSFET: L ch = 80 nm 3 nm Al 2 O 3 (EOT = 1.5 nm) I s (A/µm) V ds =0.05 V S lin = 70 mv/dec S sat = 80 mv/dec DIBL = 88 mv/v V gs (V) 8

9 Benchmark with Si/Ge VNW MOSFETs Peak g m of InGaAs (V DS =0.5 V), Si and Ge VNW MOSFETs g m,pk (µs/µm) V 1 V 1V Target 1.2 V 1.2 V Diameter (nm) Si/Ge InGaAs Our work (V DS =0.5 V) 1 InGaAs competitive with Si Need to demonstrate VNW MOSFETs with D<10 nm 9

10 InGaAs VNW Mechanical Stability for D<10 nm 8 nm InGaAs VNWs after 7 DE cycles: 8 nm InGaAs VNWs: Yield = 0% Broken NW Difficult to reach 10 nm VNW diameter due to breakage 10

11 InGaAs VNW Mechanical Stability for D<10 nm Difficult to reach 10 nm VNW diameter due to breakage Broken NW 8 nm InGaAs VNWs: Yield = 0% Water-based acid is problem: Surface tension (mn/m): Water: 72 Methanol: 22 IPA: 23 Solution: alcohol-based digital etch 11

12 Alcohol-Based Digital Etch 8 nm InGaAs VNWs after 7 DE cycles: Lu, EDL % HCl in DI water Yield = 0% 10% HCl in IPA Yield = 97% Broken NW Radial etch rate: 1.0 nm/cycle Radial etch rate: 1.0 nm/cycle Alcohol-based DE enables D < 10 nm 12

13 D=5.5 nm VNW arrays 10% H 2 SO 4 in methanol 90% yield H 2 SO 4 :methanol yields 90% at D=6 nm! Viscosity matters: methanol (0.54 cp) vs. IPA (2.0 cp) 13

14 InGaAs Digital Etch First demonstration of D=5 nm diameter InGaAs VNW (Aspect Ratio > 40) 14

15 Latest! D=15 nm InGaAs VNW MOSFET 200 Vgs = 0 V to 0.6 V in 0.1 V step I d (µa/µm) R on = 5500 Ω µm Mo contact D = 15 nm 300 o C N 2 RTA V ds (V) Single nanowire MOSFET: L ch = 80 nm 2.5 nm Al 2 O 3 (EOT = 1.3 nm) Zhao, IEDM

16 Benchmark with Si/Ge VNW MOSFETs Peak g m of InGaAs (V DS =0.5 V), Si and Ge VNW MOSFETs Our latest work (V DS =0.5 V) Target Even better results at IEDM 2017! Most aggressively scaled VNW MOSFET ever 16

17 InGaAs/InAs heterojunction VNW MIT Top-down approach: flexible and manufacturable 17

18 Gen-2 InGaAs VNW-TFET Single NW: D= 40 nm, L ch = 60 nm, 3 nm Al 2 O 3 (EOT = 1.5 nm) New step: final RTA 10 fold reduction in D it 2.0 V gs =0 V to 0.6 V in 0.1 V step 10 0 V gs = 0 V to 0.6 V in 0.1 V step I d (µa/µm) I d (µa/µm) V ds (V) V ds (V) Zhao, EDL 2017 Saturated output characteristics Clear negative differential resistance Peak to valley ratio of V gs = 0.6 V 18

19 NW-TFET subthreshold characteristics I d (A/µm) 10-5 T=300 K V d =0.3 V V d =0.05 V V gs (V) S (mv/dec) I d (A/µm) V d = 0.05 V V d = 0.3 V Sub-thermal for 2 orders of magnitude of current S lin = 55 mv/dec S sat = 53 mv/dec Zhao, EDL

20 Random Telegraph noise (RTN) in TFETs 10-5 Jump 10-6 V ds =0.3 V I d (A) 3n 2n 2n 2n 2n 2n V ds = 50 mv V gs = 0.24 V SI d /I 2 d (Hz-1 ) Welch 1/f2 1/f I d (A/µm) V ds =0.05 V S lin = 61 mv/dec S sat = 66 mv/dec V gs (V) I d (A) 1n 1n 1n 900p 800p 700p 600p 500p V ds Time [S] = 50 mv V gs = 0.18 V SI d /I 2 d (Hz-1 ) f [Hz] Welch 1/f2 1/f 400p 300p Time [S] f [Hz] RTN consistent with jump in subthreshold current Single-trap behavior visible

21 21 Conclusions Improved InGaAs etching technology: sub-10 nm nanowires with very high aspect ratio and high yield InGaAs VNW MOSFETs with record characteristics InGaAs VNW TFETs with subthermal behavior over 2 orders of magnitude of I D Exciting new results to be presented at IEDM 2017