Electronics Proliferation through Diversification of Solid-State Devices and Materials

Transcription

1 Electronics Proliferation through Diversification of Solid-State Devices and Materials Prof. Tsu-Jae King Liu Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA September 28, International Conference on Solid State Devices and Materials

2 The Information Age The Semiconductor Market*: Computers 42% Communications 24% Industrial 8% Transportation 8% IC technology advancement over the past 40+ years has had dramatic impact on the way we live, work, and play. OUTPUT (billions) Source: ICKnowledge LLC Consumer Electronics 16% Military 2% YEAR *Source: IC Insights Market Drivers 2008 *Source: IC Insights Market Drivers

3 Data center electricity use increased from 0.5% of world total in 2000 to 1% of world total in 2005 Source: J. Koomey (LBNL),

4 Better processing power + Smaller form factor + Lower prices more units # DEVICES (MM) Source: ITU, Mark Lipacis, Morgan Stanley Research YEAR 4

5 Shift to Mobile Usage 5

6 Vision for 2020: Swarms of Electronics Today s Mobile: Gateway to the Cloud Infrastructional core Sensory swarm (trillions of devices) J. Rabaey, ASPDAC 2008 Mobile access Tomorrow s Mobile: Bridge to the Swarm 6

7 Technology Drivers Driver for More of Moore s Law Still need >10x reductions in energy, size, cost Driver for More Than Moore s Law J. Rabaey, ASPDAC

8 Diversification for More of Moore s Law MOSFET structures MOSFET gate-stack materials Alternative switch designs Tunnel FET Mechanical switch III-V MOSFETs

9 Improving MOSFET Scalability 32 nm planar 22 nm thin-body beyond 10 nm nanowires? J. Kavalieros et al., VLSI 2006 C. Dupré et al., IEDM 2008 P. Packan et al., IEDM 2009 K. Cheng et al., VLSI

10 Channel-Length Scaling Limit Quantum mechanical tunneling sets a fundamental scaling limit for the channel length (L C ). If electrons can easily tunnel through the source potential barrier, the gate cannot shut off the transistor. nmosfet Energy Band Diagram (OFF state) SOURCE DRAIN E C J. Wang et al., IEDM Technical Digest, pp , 2002 E C 10

11 Ultimately Scaled MOSFET Double-Gate Ballistic MOSFETs L C = 8 nm, EOT = 0.45 nm Ballistic Si MOSFET (L C < 10 nm) K. Cantley et al., IEDM Technical Digest, pp ,

12 Reducing Parasitic Resistance K. Kuhn, IEDM Short Course 2008 A. M. Noori et al., IEEE Trans. Electron Devices pp , 2008 Advanced anneal techniques Low Schottky barrier height contacts alloy and implant approaches, dual silicide

13 Reducing Parasitic Capacitance Low-k or air spacers T.-Y. Liow et al., IEEE Electron Device Letters pp , 2008 K. Kuhn, IEDM Short Course 2008

14 CMOS Energy-Efficiency Limit 100 Combinational Logic Block Normalized Energy/op reducing V DD D Q clk Fanout: f V DD V DD V DD D Q clk /throughput (ps/op) Active Energy E total = αl αl d fcv d DD2 DD2 [1 + (LL d fi f/2α)(i OFF V DD OFF t delay /I ON )] t delay = L d fcv DD / (2I ON ) Passive Energy Logic Depth: L d A lower limit in E/op exists due to transistor OFF-state leakage. optimal I ON /I OFF L d f/ α: Activity Factor L d : Logic Depth f: Fanout C: Capacitance per Stage B. Calhoun et al., IEEE J. Solid State Circuits, Vol. 50, pp ,

15 MOSFET-Replacement Devices New Device Drain Current 1/S MOSFET Energy MOSFET New Device Gate Voltage Delay Higher I ON /I OFF ratio lower minimum Energy/op New device with steeper switching behavior needed (S < 60mV/dec) 15

16 Diversification for More of Moore s Law MOSFET structures MOSFET gate-stack materials Alternative switch designs Tunnel FET Mechanical switch III-V MOSFETs

17 Advanced Gate Stack Materials for Giant Capacitance Ferroelectric Dielectric Regular insulator Ferroelectric + Dielectric Energy, U 0 Energy, U 0 E = 1/2 Q 2 /C Energy, U 0 0 Charge, Q 0 Charge, Q 0 Charge, Q Resultant Capacitance > C S. Salahuddin et al., Nanoletters 2008 and IEDM

18 Sub-60 mv/dec MOSFET There is no limit to the amount of charge for very little energy. Depends only on the energy slopes There is no minimum gate voltage for the required current. 18

19 Negative Capacitance FET Subthreshold swing: Body factor: < 1 if C ins < 0 A. Rusu et al., IEDM

20 MOSFET vs. Tunnel FET BAND DIAGRAM STRUCTURE N+ Source Source Gate P- N+ Drain Thermionic Emission Drain E C E V P+ Source Source Gate P- N+ Drain Band-to-Band Tunneling Drain E C E V I D exp(qv GS /nkt) I D = AE S exp(-b/e S ) (E S = electric field) 20

21 Ge-Source Tunnel FET S. H. Kim et al., Symp. VLSI Technology

22 Planar Source: Partially Elevated Source: Fully Elevated Source: Ge-Source Structure Optimization I DS [A/µm] I ON /I OFF by optimizing Ge & Si thickness and doping elevating source Experimental Data Calibration Planar T Ge =15nm Partially Elevated T Ge =25nm Fully Elevated T Ge =25nm T Ge =45nm T Ge =65nm V DS = 0.5V Fully Elevated I DS [µa/µm] 60 V GS -V ON = 0.5V V DS [V] V GS [V] S. H. Kim et al., IEEE Electron Device Letters, Vol. 31, No. 10, pp , Parameter Value L G 30 nm T OX (EOT) 1 nm T BODY 100 nm T OFFSET 5nm N SRC cm 3 N BODY cm 3 N DRAIN cm 3 22

23 Energy-Performance Comparison stage FO1 inverter chains activity factor = 0.01 Energy [J] V DD V Planar T Ge =15nm Partially Elevated T Ge =25nm Fully Elevated T Ge =25nm T Ge =45nm T Ge =65nm MOSFET L G =22nm Frequency [Hz] Ge-source TFETs are projected to achieve lower E/op than CMOS below 1 GHz S. H. Kim et al., IEEE Electron Device Letters, Vol. 31, No. 10, pp ,

24 Advanced Devices & Materials for TFETs Comparison of simulated TFET I D -V GS curves T.-J. K. Liu et al., SSDM

25 Why Mechanical Switches? Zero off-state leakage zero leakage energy 3-Terminal Switch Air gap Source t gap Gate Drain t dimple Abrupt switching behavior allows for aggressive V DD scaling (ultra-low dynamic energy) Drain Current 1.E-04 1.E-06 1.E-08 1.E-10 1.E-12 1.E-14 Measured I-V S<0.1mV/dec V RL V PI Gate Voltage 25

26 Relay Reliability MCTF increases exponentially with decreasing V DD MCTF increases linearly with decreasing C L Endurance is projected to exceed cycles at V DD = 1 V H. Kam et al., IEDM

27 Digital IC Design with Relays 4 gate delays 1 mechanical delay CMOS: delay is set by electrical time constant Quadratic delay penalty for stacking devices Buffer & distribute logical/electrical effort over many stages Relays: delay is dominated by mechanical movement Can stack ~100 devices before t elec t mech Implement relay logic as a single complex gate F. Chen et al., ICCAD

28 Micro-Relay-Based VLSI Building Blocks 2010 ISSCC Jack Raper Award for Outstanding Technology Directions F. Chen et al., ISSCC

29 Energy-Delay Comparison 30-stage FO4 inverter chain: 0 V V dd Output 30-relay chain: V dd 0 V Transition probability=0.01 Cap/CMOS inverter=0.57ff Input Output Scaled relay technology is projected to provide for >10x energy savings, at clock rates up to ~100MHz V. Pott et al., Proc. IEEE, Vol. 98, pp ,

30 Diversification for More of Moore s Law MOSFET structures MOSFET gate-stack materials Alternative switch designs Tunnel FET Mechanical switch III-V MOSFETs

31 Power Distribution in Microprocessors Today: Power distribution at low voltages, high currents conductive losses Future: Power distribution at high voltages, low currents Local conversion to low voltages, high currents Memory Logic 12-to-1 V GaN/Si Converter 12 V Input Voltage Pad RF Communications I/O courtesy Tomás Palacios (MIT) 12 V power lines ~1 V power lines 31

32 Outstanding properties of AlGaN/GaN: High E br : 3.3 MV/cm High electron density: > 1x10 13 /cm 2 High mobility: > 1500 cm 2 /Vs Low C in, C out high switching speed High thermal stability n i < 1x10 7 /cm 3 at 400 o C Improved efficiency Simplified circuit designs Reduced cooling requirements Why GaN? R on (mohm-cm 2 ) Si limit W. Saito '03 AlGaN/GaN/SiC 4H-SiC limit G. Deboy '98 Si SJ MOSFET S. Harada '04 SiC DEMOSFET GaN limit N.Q. Zhang '01 AlGaN/GaN/SiC V br (V) N. Ikeda '08 AlGaN/GaN/Si Y. Dora '06 AlGaN/GaN/SiC courtesy Tomás Palacios (MIT) 32

33 Diversification for More than Moore s Law

34 Functional Diversification Both energy efficiency and functional capabilities beyond the limits of ultimately scaled CMOS will be needed for electronics to expand into new applications. Micro/Nano Electronics RF MEMS Mobile Internet Devices high speed (>2 GHz) low operating voltage low standby power Adapted from T. Skotnicki, IEDM Short Course 2010 Photonics Sensors Heterogeneous integration with CMOS compact form factor 34

35 MEMS for Wireless Communications Advantages of MEMS RF filters: small size low power low phase noise high Q courtesy Clark Nguyen (UC-Berkeley) 35

36 The Resonant Body Transistor Drive gate is biased in accumulation (V acc ). Capacitive force due to input signal (v in ) drives resonant motion. Sense gate biased to strong inversion (V G ). As the body vibrates, the drain current I D is modulated piezoresistively. RBT demonstrated at 11.7 GHz with quality factor Q of 1831 V D = 4.5 V V G = 5 V V ACC = 0.5 V P in = 20 dbm G1 S 500 nm f res = GHz Δf 3dB = 6.4 MHz Q = 1831 f res Q = D G2 Fabricated side-by-side with FinFETs To avoid the need for release, CMOS layers can be used to form acoustic Bragg reflectors to localize vibrations D. Weinstein and S. A. Bhave, Nano Letters 10(4) (2010) 36

37 Nanowire Sensor Arrays CMOS-integrated sensors for detection of chemical and biomolecular species with high sensitivity and specificity. Heterogeneous Nanowire FET Array Fabrication: courtesy Ali Javey (UC-Berkeley) 37

38 Pd/Si Nanowire H 2 Sensors Without H 2 : ohmic contact With H 2 :Schottky contact K. Skucha et al., Sensors & Actuators B, pp ,

39 Summary

40 Diversification is the Key Advanced materials Advanced devices Beyond CMOS devices & materials Courtesy Dan Armbrust, SEMATECH 40

41 A Vision of the Future J. Rabaey ASPDAC 08 The Cloud Mobile Devices The Swarm Sensatex Diversification Transistor of Devices & Materials Heterogeneous Scaling Integration Better Energy Efficiency Higher Investment & Functionality, Performance, Lower Cost Cost Market Growth Information technology will be pervasive embedded human-centered solving societal scale problems Energy Health care Environment Disaster response Philips Transportation 41

42 Faculty colleagues: Acknowledgements Jan Rabaey, Eli Yablonovitch, Elad Alon, Chenming Hu, Sayeef Salahuddin, Ali Javey, Clark Nguyen (UCB) Tomás Palacios, Vladimir Stojanović, Dana Weinstein (MIT) Dejan Marković (UCLA), Mark Lundstrom (Purdue) Graduate students: Sung Hwan Kim, Zachery Jacobson, Hei Kam, Rhesa Nathanael, Jaeseok Jeon, Matt Spencer; Fred Chen & Hossein Fariborzi (MIT), Chengcheng Wang and Kevin Dwan (UCLA) Funding:» DARPA/MARCO Focus Center Research Program: Center for Circuits and Systems Solutions (C2S2) Center for Materials, Structures, and Devices (MSD)» NSF Center of Integrated Nanomechanical Systems (COINS)» DARPA/MTO STEEP Program and NEMS Program» NSF Center for Energy Efficient Electronics Science (E3S) 42