New Devices for Ultra Low Energy Information Processing

Transcription

1 Beyond Transistor Scaling: New Devices for Ultra Low Energy Information Processing Prof. Tsu Jae King Liu Department of Electrical Engineering and Computer Sciences University it of California, i Berkeley, CA January 28, 2009

2 The Information Age The Semiconductor Market: Computers 42% Industrial 8% IC technology advancement over the past 40+ years has had dramatic impact on the way we live, work, and play. Communications 24% Transportation 8% ) OUTPU UT (billions Consumer Electronics Military YEAR 16% 2% 2

3 Outline Introduction IC technology advancement The CMOS Power Crisis New Switching Devices How did we get here? Why is there a problem? What is the solution? Summary 3

4 A Brief History of the Transistor 1940 s: Vacuum tube era Vacuum tubes were used for radios, television, telephone equipment, and computers but they were expensive, bulky, fragile, and energy hungry. Invention of the point contact transistor Walter Brattain, John Bardeen, and William Shockley, Bell Labs, 1947 Nobel Prize in Physics 1956 Reproducibility was anissue, however. Invention of the bipolar junction transistor (BJT) William Shockley, Bell Labs, 1950 Lee De ENIAC The Forest, 1906 first digital computer more stable and reliable; easier and cheaper to make 4

5 Discrete Electronic Circuits In 1954, Texas Instruments produced the first commercial silicon transistor. ~$2.50 each Before the invention of the integrated circuit, electronic equipment was composed of discrete components such as transistors, resistors, and capacitors. These components, often simply called discretes, were manufactured separately and were wired or soldered d together th onto circuit itboards. Discretes took up a lot of room and were expensive and cumbersome to assemble, so engineers began, in the mid 1950s, to search for a simpler approach 5

6 The Integrated Circuit (IC) An IC consists of interconnected electronic components in a single piece ( chip ) of semiconductor material. In 1958, Jack S. Kilby (Texas Instruments) showed that it was possible to fabricate a simple IC in germanium. In 1959, Robert Noyce (Fairchild Semiconductor) demonstrated an IC made in silicon using SiO 2 as the insulator and Al for the metallic interconnects. The first planar IC (actual size: ~1.5mm diameter) 6

7 From a Few, to Billions of Components By connecting a large number of components, each performing simple operations, an IC that performs complex tasks can be built. The degree of integration has increased at an exponential pace over the past ~40 years. The number of devices on a chip doubles every ~2 years, for the same price. Moore s Law still holds today. Intel Penryn Processor 300mm Si wafer 7

8 The MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor: Desired characteristics: High ON current Low OFF current Source Substrate GATE LENGTH, L g Gate Drain JUNCTION DEPTH, X j OXIDE THICKNESS, T ox M. Bohr, Intel Developer Forum, September 2004 Current flowing between the SOURCE and DRAIN is controlled by the voltage on the GATE electrode N channel & P channel MOSFETs operate in a complementary manner CMOS = Complementary MOS CURRENT V TH GATE VOLTAGE 8

9 CMOS Devices and Circuits CIRCUIT SYMBOLS N-channel P-channel MOSFET MOSFET G G S D S D CMOS INVERTER CIRCUIT V IN V DD V OUT S D D S GND V DD V OUT 0 V DD INVERTER LOGIC SYMBOL V IN STATIC MEMORY (SRAM) CELL WORD LINE BIT LINE BIT LINE 9

10 IC Technology Advancement Improvements in IC performance and cost have been enabled by the steady miniaturization of the transistor: Transistor Scaling Investment Better Performance/Cost 100 Market Growth PITCH YEAR: HALF-PITCH: 90nm 65nm 45nm 32nm 22nm GATE LEN NGTH (nm) 10 B. Davari, Proc. IEEE, April 1995 Int l Technology Roadmap for Semiconductors LOW POWER HIGH PERFORMANCE YEAR 10

11 The Nanometer Size Scale MOSFET Human Hair 100μm 10μm Carbon nanotube 11

12 The CMOS Power Crisis

13 Off State Leakage Current (I OFF ) log I DS leakage current, I OFF CU URRENT V TH 0 GATE V VOLTAGE TH The inverse slope is defined to be the subthreshold swing, S V GS The leakage current specification sets the lower limit for the threshold voltage V TH. 13

14 V TH Design Trade Off Low V TH is desirable for high ON current: I ON (V DD V TH ) η 1 < η < 2 where V DD is the power supply voltage but high V TH is needed for low OFF current I ON,low VTH log I DS Low V TH I ON,highVTH I OFF,low VTH High V TH I OFF,highVTH V GS 0 V DD 14

15 Historical Voltage Scaling Since V TH cannot be scaled down aggressively, the power supply voltage (V DD ) has not been scaled down in proportion to the MOSFET channel length: V DD V DD V TH Source: P. Packan (Intel), 2007 IEDM Short Course 15

16 Power Density Scaling NOT! Pow wer Density (W/cm 2 ) 1E+03 1E+02 1E+01 1E+00 1E-01 1E-02 Power Density vs. CMOS Scaling Active Power Density Gate Length (μm) Po ower Density (W/cm2) Power Density Prediction circa 2000 Sun s Surface Rocket Nozzle Nuclear Reactor E Hot Plate P6 Passive Power Density Pentium proc 1E E Year Source: B. Meyerson (IBM) Semico Conf., January 2004 Source: S. Borkar (Intel ) courtesy L. Pileggi 16

17 Minimizing Operation Energy CMOS Energy per Operation 100 CMOS Energy vs. Delay Normalized Energy/op E 60 total E E dynamic leakage /throughput (ps/op) E dynamic + E leakage = αl d CV dd2 + L d I OFF V dd t delay t delay = L d CV dd /(2I ON ) CMOS has a fundamental lower limit in energy per operation, due to subthreshold leakage. 17

18 Parallelism to Recover Performance 100 ity (W/cm2) Power Dens Sun s Surface Rocket Nozzle Nuclear Reactor 8086 Core Hot Plate P Pentium proc Year Source: S. Borkar (Intel ) ormalized En nergy/op N Run in parallel to recoup performance Operate at a lower energy point /throughput (ps/op) Computing performance is now limited by power dissipation. This has forced the move to parallelism as principal means of increasing performance without increasing energy per operation. 18

19 The Need for a New Switch CMOS Energy vs. Delay (normalized) Today: Parallelism lowers E/op Future: Parallelism doesn t help Delay When each core operates at the minimum i energy, increasing performance requires more power. 19

20 New Switching Devices

21 Breaking the Thermal (kt/q) Limit n(e) exp ( E/kT) Electron Energy Band Profile log I D I ON g E increasin S I OFF VDD V G distance In the subthreshold region (V GS < V TH ), I S 60mV/dec at room temperature D qvgs exp nkt S must be reduced in order to achieve the desired I ON /I OFF with smaller V DD 21

22 Tunneling FET Structure: Gate Si TFET I-V Characteristics W. Y. Choi et al. (Seoul Nat l U. & UC Berkeley) IEEE EDL vol. 28,, pp , 2007 Energy-band Diagrams: OFF STATE: ON STATE: p+ Source n+ Drain Substrate E C E V E C E V bandgap gp( (E g g) tunneling current I D = aξ exp( b / ξ ) t (A/μm) Drain Curren V D =1 V V D = 0.1 V SS = 52.8 mv/dec 10-7 T = 300 K L 10-8 G = 70 nm t ox = 2 nm 10-9 t SOI = 70 nm W = 10 μm Gate Voltage (V) ξ = a V + V A GS κt ox tunnel m * / E g b m * / E 3 g 22

23 Energy Performance Comparison H. Kam et al. (UCB, Stanford U) U.), 2008 IEDM Energy [J] 1E15 1.E-15 1.E-16 1.E-17 CMOS TFET Si TFETs appear promising for sub 1GHz applications 1.E-18 1.E-02 1.E-01 1.E+00 1.E+01 Performance (GHz) 30-stage 65nm CMOS inverter chain (transition probability=0.01, capacitance per stage=2.4ff) 23

24 TFET Technology Challenges Increased I ON to expand range of applications Advanced d semiconductor materials to achieve smaller effective E g V TH control TFET based integrated circuit design

25 A Blast from the Past Charles Babbage s Difference Engine No. 2 (designed between 1847 and 1849) Digicomp mechanical computer (1960 s) 8,000 parts of bronze, cast iron, and steel five tons 11 feet long and 7 feet high On display at the Computer History Museum (Mountain View, CA) 25

26 MEMS Technology Surface Micromachining (cross sectional view) structural film sacrificial i layer Si wafer substrate Mechanical structures can be made using conventional microfabrication i i techniques Structures are freed by selective removal of sacrificial layer(s) Mechanical structures can be fabricated with a low thermal budget, suited for modular integration with CMOS electronics. 26

27 DMD TM Projection Display Chip Texas Instruments Inc. Micro mirrors are made using metal layers (Al, alloys) sacrificial i material lis photoresist t SEM image of pixel array Schematic of 2 pixels Each mirror corresponds to a single pixel,,programmed by an underlying memory cell to deflect light either into a projection lens or a light absorber. 27

28 MOSFET Inspired Relay Design OFF-state V GB < V TH F. Chen et al. (MIT, UCB, UCLA), 2008 ICCAD ON-state V GB V TH The mechanical gate is electrostatically actuated by a voltage applied between the gate and body electrode, to bring the channel into contact with the source and drain electrodes. Plan View Micrograph Measured I V 1.E-2 Ideal switching behavior: Zero off state leakage Abrupt turn on low V TH (and V DD ) possible! (A) I DS 1.E-6 1.E-10 1.E-14 V DS = 0.5V V Body =0V Gate: W =2μm L=20μm H =200nm actuation gap = 400nm V GB (V) L 28

29 Relay Scaling F. Chen et al. (MIT, UCB, UCLA), 2008 ICCAD Scaling has similar benefits for relays as for MOSFETs Pull in Voltage with Beam Scaling Measured pull involtages scale linearly {W,L,t gap } = {90nm,2.3um,10nm} V pi = 200mV Mechanical delay also scales linearly 29

30 Energy Performance Comparison F. Chen et al. (MIT, UCB, UCLA), 2008 ICCAD Relays have small RC delay but large mechanical delay Complete all logic in a single complex (pass transistor) gate Relay Full Adder Cell Energy vs. delay comparison V DD generate C in a propagate a b a b a V DD C out V DD 90nm CMOS 10x b_b S b kill a V DD a_b a b kill C in b propagate a b generate C out A relay adder can be ~10x more energy efficient at the same delay and layout area as a CMOS adder. 30

31 Relay Technology Challenges Surface adhesion force Mechanical contact resistance Relay I-V Characteristic Reliability I DS hysteresis due I to surface force V rel V pi V GS

32 Enabling Radio on a Chip Massive Cluster Gigabit Ethernet Clusters Integration trend for mobile phones MEMSenabled single-chip radio wireless sensor network Advantages of MEMS RF filters: small size low power low phase noise high Q Timing reference can also be implemented on-chip with MEMS courtesy 32 of Robert Aigner (Infineon Technologies) 32

33 Summary

34 Summary Due to subthreshold leakage, CMOS technology has a fundamentallimitinenergy limit in energy efficiency. New switching devices with steeper turn on behavior are needed to achieve substantially lower energy per operation. Examples: tunneling FET, relay Note: Such devices may have very different characteristics than the MOSFET. Thus, they will require new circuit and system architectures to fully realize their potential energyefficiency (and hence performance) benefits. 34

35 The Age of Ubiquitous Computing LES($)/YR SA Mainframes (>1 persons per computer) PCs (1 person/computer) p UbiComp (>1 computers per person) Acknowledgement: Mark Weiser TIME Sensatex Philips today Investment Technology, Device & Circuit Transistor Innovations, Scaling Heterogeneous Integration Higher Lower Performance, Power, Lower Cost Market Growth Information technology will for better quality of life pervasive embedded 200% human centered since 1990 solving societalscale Energy Health 40% problems care Transportation $370 Billion Total U.S. Annual Energy Costs Environment Increase in U.S. Electricity Consumption Disaster response Total U.S. Energy Consumption for Buildings 72% Total U.S. Electricity Consumption for Buildings 55% Total U.S. Natural Gas Consumption for Buildings 35

36 Acknowledgements Collaborators: Faculty: Elad Alon (UCB), Dejan Markovic (UCLA), VladimirStojanovic (MIT) Post doctoral researcher: Woo Young Choi (Sogang U.) Students: Hei Kam, Fred Chen (MIT) Funding:» DARPA STEEP Program» DARPA/MARCO Focus Center Research Program: Center for Circuits and Systems Solutions (C2S2) Center for Materials, Structures, and Devices (MSD) UC Berkeley MicrofabricationLaboratory 36