IH2655 Design and Characterisation of Nano- and Microdevices. Lecture 1 Introduction and technology roadmap
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1 IH2655 Design and Characterisation of Nano- and Microdevices Lecture 1 Introduction and technology roadmap
2 IH2655 Design and Characterisation of Nano- and Microdevices Introduction to IH2655 Brief historic overview Moore s Law and the ITRS Roadmap MOS Transistor (re-cap) From Geometrical to Material-based scaling CMOS Process Flow
3 IH2655 SPRING 2013 Course PM Subject: Advanced course of the physical and technological concepts used in modern CMOS and bipolar/bicmos fabrication. Prerequisites: Semiconductor Devices (IH1611) or Semiconductor Theory and Device Physics (IH2651) or equivalent knowledge in semiconductor device physics. Course content: 26 h lectures week 3-10 (see Daisy schedule). Approximately 8 h laboratory exercises (2 labs), to be scheduled in groups of 4-5. Language: English
4 IH2655 SPRING 2013 Course PM cont d Lecturer and Course Director: Prof. Mikael Östling, Department of Integrated Devices & Circuits (EKT), School of ICT, KTH. ostling@kth.se, phone: Lectures will also be given by: Dr Christoph Henkel , chenkel@kth.se and Assoc. prof Gunnar Malm, gunta@kth.se, , same department Laboratory asisstants are Mr Eugenio Dentoni Litta, eudl@kth.se, and Mr Sam Vaziri, vaziri@kth.se, same department. Literature: Plummer, Deal and Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling. Prentice-Hall 2000, ISBN (725 kr THS Bookstore in Kista) Examples from other VLSI books and journal articles Strong Suggestion: Read chapters before class Concept Tests will help you much more Examination: Two written lab reports on time and 1 h Oral examination. Signup sheets for labs and exam through Daisy.
5 Course PM cont d NOTE: LAB REPORTS ARE DUE ONE WEEK AFTER THE LAB! IF YOUR LAB REPORT IS LATE YOUR MAXIMUM GRADE IS E Individual laboratory reports are required and please observe that any signs of plagiarism will directly be reported to the Disciplinary board
6 IH2655 SPRING 2013 Schedule # Date Time Room Subject 1 14-Jan Ka439 Introduction. MOSFETs,Technology roadmap. Overview of fabrication flow (M Östling) 2 15-Jan Ka439 Wafer fabrication and silicon epitaxy (M Östling) 3 21-Jan Ka439 Wafer clean and wet processing, (C Henkel) 4 22-Jan Ka439 Electrical characterization. (G Malm) 5 28-Jan Ka439 Thermal oxidation of silicon (C Henkel) 6 29-Jan Ka439 Annealing (FA & RTA) Diffusion and ion implantation, (C Henkel) 7 4-Feb Ka439 Dry etching (M Östling) 8 5-Feb Ka439 Deposition of dielectrics and polysilicon (C Henkel) 9 11-Feb Ka439 Microlithography (M Östling) Feb Ka439 Metallization and contacts (M Östling) Feb Ka439 Back-end processing (M. Östling) Feb Ka439 Process integration: MOS and Bipolar Feb Ka439 Sustainable fabrication (G Malm) Mar Ka439 Nanostructures / nanophysics (M Östling) 15 4-Mar Ka439 Reserve time Mikael Östling KTH
7 IH2655 SPRING 2013 Microelectronic processing Clean room environment Wafer level Source: Infineon Source: Infineon SiO 2 source gate drain Transistor level Chip level so why should you care if you plan to work in Nanoscience, MEMS, PV or Photonics?
8 IH2655 SPRING 2013 Top down AND Bottom Up Source: website Univ. Wien
9 IH2655 SPRING 2013 IH2655: Lego for grown-ups wafer KTH KTH Baba, Nature Photonics 3, (2009)
10 IH2655 SPRING 2013 IH2655 Aim This course is about the process technology used to manufacture semiconductor devices. It aims to familiarize with the related technical vocabulary and to provide the students with a tool kit of fabrication methods for a range of devices. After the course the student should be able to describe the technological processes involved in the fabrication of nano- and microelectronic devices and circuits compare alternative fabrication methods apply the knowledge to specific device requirements through careful selection among a number of choices assess pros and cons of different fabrication methods combine fabrication methods to develop complex process flows for functional devices and circuits in a range of applications (e.g. transistors, solar cells, optoelectronics...)
11 IH2655 SPRING 2013 Introduction to IH2655 Brief historic overview Moore s Law and the ITRS Roadmap MOS Transistor (re-cap) From Geometrical to Material-based scaling CMOS Process Flow
12 IH2655 SPRING 2013 Brief retrospect:a great invention based on Sciences Bardeen, Brattain, Shockley, First Ge-based bipolar transistor invented 1947, Bell Labs. Nobel prize 1956 Atalla, First Si-based MOSFET invented 1958, Bell Labs. Kilby (TI) & Noyce (Fairchild), Invention of integrated circuits 1959, Nobel prize Planar technology, Jean Hoerni, Fairchild, 1960 First CMOS invented early 1960 s Moore s law coined 1965, Fairchild Dennard, scaling rule presented 1974, IBM First Si technology roadmap published 1994, USA
13 Bardeen, Brattain, Shockley, First Ge-based bipolar transistor invented 1947, Bell Labs. Nobel prize st point contact transistor -- by Bell Lab J. Bardeen W. Brattain W. Shockley Polycrystalline Ge 1956 Nobel Physics Prize Transistor=transfer + resistor --Transferring electrical signal across a resistor
14 Kilby (TI) & Noyce (Fairchild), Invention of integrated circuits 1959, Nobel prize
15 Kilby (TI) & Noyce (Fairchild), Invention of integrated circuits 1959, Nobel prize This marked the start of an amazing development -> Increasing integration of components
16 Planar process Planar technology, Jean Hoerni, Fairchild, 1960 Invented by Jean Hoerni at Fairchild Semiconductor (late 50's)
17 NMOS technology Dennard, scaling rule presented 1974, IBM
18 First Si technology roadmap published 1994, USA Started by Semiconductor Industry Association (SIA) in USA 1994: creation of an American style roadmap The National Technology Roadmap for Semiconductors (NTRS) 1998, the SIA became closer to its European, Japanese, Korean and Taiwanese counterparts by creating the first global roadmap The International Technology Roadmap for Semiconductors (ITRS). Today: Over 1000 companies and research institutions
19 First Si technology roadmap published 1994, USA Started by Semiconductor Industry Association (SIA) in USA 1994: creation of an American style roadmap The National Technology Roadmap for Semiconductors (NTRS) 1998, the SIA became closer to its European, Japanese, Korean and Taiwanese counterparts by creating the first global roadmap The International Technology Roadmap for Semiconductors (ITRS). Today: Over 1000 companies and research institutions Teams for: System Drivers Design Test & Test Equipment Process Integration, Devices, & Structures RF and A/MS Technologies for Wireless Communications Emerging Research Devices Emerging Research Materials Front End Processes Lithography Interconnect Factory Integration Assembly & Packaging Environment, Safety, & Health Yield Enhancement Metrology Modeling & Simulation
20 Introduction to IH2655 Brief historic overview Moore s Law and the ITRS Roadmap From Geometrical to Material-based scaling CMOS Process Flow
21 Moore s law : coined 1965, Fairchild Gordon Moore s original Ideas in 1965 Source; Intel
22 Moore s law : coined 1965, Fairchild 1965: Components per integrated function Source: G.E. Moore, Cramming more components onto integrated circuits, Electronics, Volume 38, Number 8, April 19, 1965
23 Moore s law : rewritten in 1975, INtel 1975: Transistors per chip. Basis: Exponential behavior Source: G.E. Moore, No exponential is forever, ISSCC, February 2003
24 Moore s law : the real motivation... Driven by $$$... Source: G.E. Moore, No exponential is forever, ISSCC, February 2003
25 Moore s law : enabled by scaling Source: G.E. Moore, No exponential is forever, ISSCC, February 2003
26 IH2655 SPRING 2013 Moore s law : enabled by scaling Pentium 4 10 µm 1 µm 0.1 µm Human hair Red blood cell Bacteria Virus MOSFET
27 IH2655 SPRING 2013 Moore s law : enabled by scaling MOSFET metrics provide additional advantage A simple model for I Don is given by the MOSFET Square-Law Equation: I Don = (W/L) (µ ox /t ox ) (V GS -V T ) 2 Chips are faster if the gate length L is reduced
28 IH2655 SPRING 2013 Moore s law : enabled by scaling IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 4, NO. 2, MARCH 2005, p153 Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor Applications Robert Chau et al
29 Moore s law : still going strong in 2010 Transistors are found in processors, memories etc. Number of transistors grows exponentially, approaching 1,000,000,000! Continuous down-scaling of transistor dimensions Source: Intel
30
31 Moore s law : However! (or: The notorious e ) Costs are rising exponentially, too!!! Source: G.E. Moore, No exponential is forever, ISSCC, February 2003
32 Moore s law : and its consequences limited by power dissipation.??? Source: G.E. Moore, No exponential is forever, ISSCC, February 2003
33 Moore s law : and its consequences Yes, if P. continues exponentially! Quelle: Intel Source: G.E. Moore, No exponential is forever, ISSCC, February 2003
34 Moore s law : not Source: G.E. Moore, No exponential is forever, ISSCC, February 2003
35 ITRS Roadmap Moore s Heirs Started by Semiconductor Industry Association (SIA) in USA 1994: creation of an American style roadmap The National Technology Roadmap for Semiconductors (NTRS) 1998, the SIA became closer to its European, Japanese, Korean and Taiwanese counterparts by creating the first global roadmap The International Technology Roadmap for Semiconductors (ITRS). Today: Over 1000 companies and research institutions Teams for: System Drivers Design Test & Test Equipment Process Integration, Devices, & Structures RF and A/MS Technologies for Wireless Communications Emerging Research Devices Emerging Research Materials Front End Processes Lithography Interconnect Factory Integration Assembly & Packaging Environment, Safety, & Health Yield Enhancement Metrology Modeling & Simulation
36 ITRS Roadmap
37 Introduction to IH2655 Brief historic overview Moore s Law and the ITRS Roadmap MOS Transistor (re-cap) From Geometrical to Material-based scaling CMOS Process Flow
38 IH2655 SPRING 2013 Long-channel MOSFETs Mikael Östling KTH
39 IH2655 SPRING 2013 MOSFET I-V characteristics Linear region (small values of V ds ): Mikael Östling KTH
40 IH2655 SPRING 2013 MOSFET I-V characteristics Mikael Östling KTH
41 IH2655 SPRING 2013 MOSFET I-V characteristics Saturation region (V ds larger than V dsat ): Mikael Östling KTH
42 IH2655 SPRING 2013 MOSFET I-V characteristics Mikael Östling KTH
43 IH2655 SPRING 2013 MOSFET I-V characteristics Mikael Östling KTH
44 IH2655 SPRING 2013 MOSFET I-V characteristics Mikael Östling KTH
45 IH2655 SPRING 2013 MOSFET I-V characteristics Mikael Östling KTH
46 IH2655 SPRING 2013 Subthreshold characteristics Mikael Östling KTH
47 IH2655 SPRING 2013 Subthreshold characteristics Mikael Östling KTH
48 IH2655 SPRING 2013 Subthreshold characteristics Mikael Östling KTH
49 IH2655 SPRING 2013 Channel mobility Mikael Östling KTH
50 IH2655 SPRING 2013 Channel mobility Mikael Östling KTH
51 IH2655 SPRING 2013 Channel mobility Mikael Östling KTH
52 IH2655 SPRING 2013 Short-channel effect (SCE) Mikael Östling KTH
53 IH2655 SPRING 2013 Short-channel effect (SCE) Mikael Östling KTH
54 IH2655 SPRING 2013 Short-channel effect (SCE) Mikael Östling KTH
55 IH2655 SPRING 2013 Constant-field scaling Mikael Östling KTH
56 IH2655 SPRING 2013 Rules for constant-field scaling NOTE: C ox is F/cm 2 Mikael Östling KTH
57 IH2655 SPRING 2013 Rules for constant-field scaling Chapter 3 Mikael Östling KTH
58 IH2655 SPRING 2013 Generalized scaling Mikael Östling KTH
59 IH2655 SPRING 2013 Rules for generalized scaling Mikael Östling KTH
60 IH2655 SPRING 2013 Nonscaling effects Thermal voltage does not scale => subthreshold nonscaling Bandgap does not scale => depletion layer does not scale Voltage level not scaled (E increases) => mobility decreases Higher electric field => higher power and lower reliability Source/Drain doping can not be scaled => higher resistance
61 Introduction to IH2655 Brief historic overview Moore s Law and the ITRS Roadmap MOS Transistor (re-cap) From Geometrical to Material-based scaling CMOS Process Flow
62 Moore s law : scaling parameters MOSFET metrics provide additional leverage: Materials A simple model for I Don is given by the MOSFET Square-Law Equation: geometric I Don = (W/L) (µ ox /t ox ) (V GS -V T ) 2 Gate length Gate width Geometric scaling is determined by improvements in process technology
63 Geometric Scaling: Isolation modules 1/2 LOCOS (semirecessed) Recessed oxidation (ROX) (fully recessed) Pros: Con: Improved geometric scalability Higher device density Increased process complexity
64 Geometric Scaling: Isolation modules 2/2 Bird s head and beak in LOCOS and ROX exhibit m encroachment Further process technology improvements Shallow Trench Isolation (STI) High-density plasma fills etched and lineroxidixed trenches with SiO 2 Hard mask layers Thermally grown, high quality liner oxide Deep-trench isolation Trench isolation can be combined with silicon-on-insulator (SOI) wafers for nearly complete device isolation Deposited, low quality filler oxide Chemical Mechanical polishing planarization
65 Moore s law : still going strong in 2010 Why? Industry guy Researcher Happy Scaling Gilbert Declerck VLSI Symp Materials based scaling Source: G.E. Moore, No exponential is forever, ISSCC, February 2003 SOI High-k Metal Gates Strained Silicon Germanium Carbon Nanotubes Graphene(!)
66 Moore s law : old & new scaling parameters MOSFET metrics provide additional leverage: Materials A simple model for I Don is given by the MOSFET Square-Law Equation: I Don = (W/L) (µ ox /t ox ) (V GS -V T ) 2 old new geometric material Gate length Gate width Mobility Dielectric constant Oxide thickness All scaling parameters are determined by improvements in process technology
67 Moore s law : still going strong in 2010 Why? Source: fabtech.org / Sigma Aldrich Today: New materials in connection with improvements in process technology
68 IH2655 SPRING 2013 Strained silicon & SiGe A transistor built with strained silicon. The silicon is stretched out because of the natural tendency for atoms inside compounds to align with one another. When is silicon is deposited on top of a substrate with atoms spaced farther apart, the atoms in silicon stretch to line up with the atoms beneath, stretching straining the silicon. In the strained silicon, electrons experience less resistance and flow up to 70 percent faster, which can lead to chips that are up to 35 percent faster without having to shrink them. Image Reproduced with Permission of IBM Almaden Research Center, IBM.
69 Intel 45nm dual-core processor die
70 Processors on an Intel 45nm Hafnium-based High-k Metal Gate ''Penryn'' Wafer photographed with an original Intel Pentium processor die. Using an entirely new transistor formula, the new processors incorporate 410 million transistors for each dual core chip, and 820 million for each quad core chip. The original Intel Pentium Processor only has 3.1 million transistors.
71
72 Introduction to IH2655 Brief historic overview Moore s Law and the ITRS Roadmap From Geometrical to Material-based scaling CMOS Process Flow
73 CMOS structures
74 CMOS Process Flow Substrate selection: moderately high resistivity, (100) orientation, P type. Wafer cleaning Thermal oxidation ( 40 nm) Silicon Nitride LPCVD deposition ( 80 nm) Photoresist spinning and baking ( μm)
75 CMOS Process Flow Mask #1 patterns the active areas Silicon Nitride is dry etched Photoresist is stripped
76 CMOS Process Flow Field oxide is grown using a LOCOS/ROX process Typically C in H 2 O grows 0.5 μm
77 CMOS Process Flow Mask #2 blocks a B + implant to form the wells for the NMOS devices Typically cm KeV
78 CMOS Process Flow Mask #3 blocks a P + implant to form the wells for the PMOS devices Typically cm KeV
79 CMOS Process Flow Annealing A high temperature drive-in produces the final well depths and repairs implant damage Typically C C
80 CMOS Process Flow Mask #4 is used to mask the PMOS devices An Implant is done on the NMOS devices Typically a 1-5 x cm -2 B KeV
81 CMOS Process Flow Mask #4 is used to mask the PMOS devices A V TH adjust implant is done on the NMOS devices Typically a 1-5 x cm -2 B KeV
82 CMOS Process Flow Mask #5 is used to mask the NMOS devices A V TH adjust implant is done on the PMOS devices, Typically 1-5 x cm -2 As KeV.
83 CMOS Process Flow The thin oxide over the active regions is stripped A high quality gate oxide grown Typically 3-5 nm, which could be grown in C in O 2 Note: Today this could be entirely different for high end technology (high-k)
84 CMOS Process Flow Polysilicon is deposited by LPCVD ( 0.5 μm) An unmasked P + or As + implant dopes the poly (typically 5 x cm -2 ) Note: Today this could be a metal gate
85 CMOS Process Flow Mask #6 is used to protect the MOS gates The poly is plasma etched using an anisotropic etch
86 CMOS Process Flow Mask #7 protects the PMOS devices A P + implant forms the LDD regions in the NMOS devices Typically 5 x cm 50 KeV
87 CMOS Process Flow Mask #8 protects the NMOS devices A B + implant forms the LDD regions in the PMOS devices Typically 5 x cm 50 KeV
88 CMOS Process Flow Conformal layer of SiO 2 is deposited (typically 0.5 μm)
89 CMOS Process Flow Anisotropic etching leaves sidewall spacers along the edges of the poly gates
90 CMOS Process Flow Mask #9 protects the PMOS devices An As + implant forms the NMOS source and drain regions Typically 2-4 x cm 75 KeV
91 CMOS Process Flow Intermetal dielectric and second level metal are deposited and defined in the same way as level #1. Mask #14 is used to define contact vias and Mask #15 is used to define metal 2 A final passivation layer of Si 3 N 4 is deposited by PECVD and patterned with Mask #16 This completes the CMOS structure
92 CMOS Process Flow Final result of the process flow: One NMOS and one PMOS device, BUT... They were made in parrallel and we can make 1 Billion other at the same time
Integrated Circuit Technology (Course Code: EE662) Lecture 1: Introduction
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