ECE 2300 Digital Logic & Computer Organization
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1 ECE 2300 Digital Logic & Computer Organization Spring 2018 CMOS Logic Lecture 4: 1
2 NAND Logic Gate X Y (X Y) = NAND Using De Morgan s Law: (X Y) = X +Y X X X +Y = Y Y Also a NAND We can build circuits from NAND only! Lecture 4: 2
3 We Can Build Circuits from NAND Only! NOT AND OR Lecture 4: 3
4 NOR Logic Gate X Y X+Y (X+Y) = NOR Using De Morgan s Law: (X+Y) = X Y X X X Y = Y Y Also a NOR We can build circuits from NOR only! Lecture 4: 4
5 Sum-of-Products Revisited AND-OR NAND-NAND Lecture 4: 5
6 Product-of-Sums Revisited OR-AND NOR-NOR Lecture 4: 6
7 A Little Bit of History Transistors Invented by John Bardeen, Walter Brattain, and William Shockley at Bell Labs in 1947 Integrated circuits Independently developed by Jack Kilby (at TI) and Robert Noyce (at Fairchild) in the 1950s Noyce and Gordon Moore founded Intel in 1968 TABLE 1. INTEL PROCESSORS, PROCESSOR INTRO DATE PROCESS TRANSISTORS FREQUENCY mm 2, KHz mm 6,000 2 MHz mm 29, MHz mm 134, MHz mm 275, MHz Intel 486 DX mm 1.2 M 33 MHz Pentium mm 3.1 M 60 MHz Source: Patrick Gelsinger, Desmond Kirkpatrick, Avinoam Kolodny, and Gadi Singer. "Such a CAD!." IEEE Solid-State Circuits Magazine, Lecture 4: 7
8 Era of Billion-Transistor Chips Apple A11 ~4B transistors Intel Haswell-EP Xeon E5 ~7B transistors IBM Power9 ~8B transistors Oracle SPARC M7 ~10B transistors NVIDIA V100 Pascal ~21B transistors Intel/Altera Stratix 10 ~30B transistors Lecture 4: 8
9 MOS Transistors Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETS) MOS transistors for short source L W gate drain gate source drain Carriers (holes or electrons) A 3-terminal device controlled by the gate voltage that acts like a switch Extreme changes in resistance (0 to ) make transistors act like switches VIN Lecture 4: 9
10 NOT Gate Input & Output Voltages A Y A Y A Y 0 1 L H 0V 5V 1 0 H L 5V 0V When the input voltage is low, the output should be connected to the voltage supply (e.g., V DD, V CC ) When the input voltage is high, the output should be connected to ground (i.e., GND) Lecture 4: 10
11 NOT Using Switches A Y A Y A Y 0 1 L H 0V 5V 1 0 H L 5V 0V Can build a NOT using two types of switches Type 1: Closed when input = 0, open when input = 1 Type 2: Closed when input = 1, open when input = 0 Lecture 4: 11
12 NAND Using Switches 5V A Inputs B Output Y Type 1: closed L L H Y = H A = L Type 2: open B = L Lecture 4: 12
13 NAND Using Switches 5V A Inputs B Output Y H L H Y = H A = H B = L Lecture 4: 13
14 NAND Using Switches 5V A Inputs B Output Y H H L Y = L A = H B = H Lecture 4: 14
15 MOS Transistors Current flows when ON (conducting) No current flows when OFF (not conducting) Type 1 and Type 2 switches G S PMOS or p-channel D S Type 1 Type 2 G D NMOS or n-channel Bubble: LOW closes the switch G: Gate; S: Source; D: Drain Lecture 4: 15
16 MOS Transistors PMOS Closed when input is low [1] Open when input is high Passes a good one (but a poor zero) [2] NMOS Closed when input is high [1] Open when input is low Passes a good zero (but a poor one) [2] G G S D D S PMOS and NMOS have complementary properties [1] In both cases, the voltage difference between the gate and source must exceed certain threshold voltage before the the transistor starts having any effect [2] Optional reading: vlsimsee.blogspot.com/2013/05/why-cant-nmos-pass-1-and-pmos-pass-0.html Lecture 4: 16
17 CMOS Logic Gates Complementary MOS (CMOS) CMOS dominates the digital IC market V DD Uses both NMOS and PMOS devices such that there is no direct supply-ground path Dissipates little power when the inputs don t change P N Our focus: Static CMOS gates Other types exist as well (pseudo- NMOS, domino,...) GND Lecture 4: 17
18 CMOS Inverter V DD V in V out G S T1 V in G D D T2 V out V in is high T1 is off T2 is on Vout is low S V in is low T1 is on T2 is off Vout is high Lecture 4: 18
19 CMOS NAND Gate Lecture 4: 19
20 3 Input CMOS NAND Gate An n-input NAND uses 2n transistors Lecture 4: 20
21 Exercise: A Mystery Gate (1) Fill out the missing entries in the above table (on/off); (2) Identify the logic gate that is implemented by the CMOS network Lecture 4: 21
22 2-Input AND Gate CMOS gates produce inherent inversion Need to add an inverter to a 2-Input NAND to form AND gate Lecture 4: 22
23 Structure of Transistor Networks Two complementary networks: A pull-up network composed of PMOS, with sources tied to voltage supply Pull-up network A pull-down network composed of NMOS, with sources tied to ground Equal number of NMOS and PMOS transistors Pull-down network Lecture 4: 23
24 Structure of Transistor Networks The pull-up and pull-down networks are always duals Parallel subnet To construct the dual of a network: Exchange NMOS for PMOS (and vice versa) Exchange series subnets for parallel subnets (and vice versa) This transformation applies to hierarchical structures Series subnet Lecture 4: 24
25 Duality of Parallel/Series Subnets A F B Pull-down series subnet F pulls down to 0 when A and B are high => F = (A B) A F Pull-up parallel subnet F pulls up to 1 when A or B is low => F = A +B = (A B) B A Pull-down parallel subnet F pulls down to 0 when A or B is high => F = (A+B) F B A B F Pull-up series subnet F pulls up to 1 when A and B are low => F = A B = (A+B) Lecture 4: 25
26 Analysis of Transistor Networks Transistor states Determine all possible input combinations Figure out the state of each transistor Determine final output or by inspection Figure out what input combinations cause a 1 (or a 0) output Lecture 4: 26
27 Analysis of Transistor Networks Build the truth table INPUTS A B C TRANSISTORS Q1 Q2 Q3 Q4 Q5 Q6 OUTPUT Z Lecture 4: 27
28 Analysis of Transistor Networks By inspection Inspect either pull-up (PMOS) or pull-down (NMOS) network Translate the series (parallel) subnets into product (sum) terms For pull-down network, negate the combined expression Pull-up: (A +B )C Pull-down: (A B + C) Lecture 4: 28
29 Recipe for Constructing CMOS Gate F = (A(B+C)) Step 1. Figure out pulldown network that does what you want (e.g., what combination of inputs generates a low output) B A C Step 3. Combine PMOS pull-up network from Step 2 with NMOS pull-down network from Step 1 to form fully-complementary CMOS gate. A B C Step 2. Walk the hierarchy replacing NMOS with PMOS, series subnets with parallel subnets, and parallel subnets with series subnets A B C B A C Lecture 4: 29
30 CMOS Sanity Checks Equal number of NMOS and PMOS NMOS sources tied to ground or to drain of another NMOS PMOS sources tied to Vdd or drain of another PMOS Inputs tied to pairs of PMOS and NMOS transistors Lecture 4: 30
31 A More Complicated Circuit Lecture 4: 31
32 Next Time Combinational Building Blocks Lecture 4: 32
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