Silicon VLSI Technology. Fundamentals, Practice and Modeling. Class Notes For Instructors. J. D. Plummer, M. D. Deal and P. B.

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1 Silicon VLSI Technology Fundamentals, ractice, and Modeling Class otes For Instructors J. D. lummer, M. D. Deal and. B. Griffin These notes are intended to be used for lectures based on the above text. They can be printed directly to make viewgraphs for use in class, and/or hardcopies for handouts to students. The notes follow the material in the text but do not cover all topics in the text. These notes are used as the basis for a one quarter long course at Stanford University taught by the authors. To allow flexible use of these notes (additions or subtractions by individual instructors), we have included page breaks after many major sections. This allows individual instructors to easily delete entire sections or to insert new sections that they create. The notes use Times 18 bold font. Comments or suggestions on these notes are welcome by to plummer@ee.stanford.edu, deal@ee.stanford.edu or griffin@stanford.edu. SILICO VLSI TECHOLOGY by rentice Hall Fundamentals, ractice and Modeling Upper Saddle River, J. By lummer, Deal and Griffin

2 ITRODUCTIO - Chapter 1 in the Text This course is basically about silicon chip fabrication, the technologies used to manufacture ICs. We will place a special emphasis on computer simulation tools to help understand these processes and as design tools. These simulation tools are more sophisticated in some technology areas than in others, but in all areas they have made tremendous progress in recent years. 1960s and early 1990s integrated circuits. rogress due to: Feature size reduction - 0.7X/3 years (Moore s Law). Increasing chip size - 16% per year. Creativity in implementing functions. SILICO VLSI TECHOLOGY by rentice Hall Fundamentals, ractice and Modeling Upper Saddle River, J. By lummer, Deal and Griffin

3 Year of 1st DRAM Shipment Minimum Feature Size 250 nm 180 nm 130 nm 100 nm 70 nm 50 nm DRAM Bits/Chip 256M 1G 4G 16G 64G 256G DRAM Chip Size (mm 2 ) Microprocessor 11M 21M 76M 200M 520M 1.40B Transistors/chip Maximum Wiring Levels Minimum Mask 22 22/ /26 26/28 28 Count Minimum Supply Voltage (volts) SIA TRS (selected data). Feature Size 100 µm 10 µm Integrated Circuit History 1 µm 0.1 µm 0.25µ in 1997 TRS Roadmap 10 nm 1 nm Transition Region Quantum Devices Atomic Dimensions 0.1 nm Year History and future projections for minimum feature size in silicon chips. Device limits appear today to be 25 nm (250 Å) channel lengths in MOS transistors. SILICO VLSI TECHOLOGY by rentice Hall Fundamentals, ractice and Modeling Upper Saddle River, J. By lummer, Deal and Griffin

4 (Reprinted with permission of IBM.) 1990 IBM demo of Å scale lithography. Technology appears to be capable of making structures much smaller than currently known device limits. Historical erspective How did we get to today s planar technology? (Reprinted with permission of Lucent Technologies). Invention of the bipolar transistor , Bell Labs. Shockley s creative failure methodology. SILICO VLSI TECHOLOGY by rentice Hall Fundamentals, ractice and Modeling Upper Saddle River, J. By lummer, Deal and Griffin

5 Grown junction transistor technology of the 1950s. In In Alloy junction technology of the 1950s. SILICO VLSI TECHOLOGY by rentice Hall Fundamentals, ractice and Modeling Upper Saddle River, J. By lummer, Deal and Griffin

6 Double diffused transistor technology of the 1950s. Si O2 The planar process (Hoerni - Fairchild, late 1950s). SILICO VLSI TECHOLOGY by rentice Hall Fundamentals, ractice and Modeling Upper Saddle River, J. By lummer, Deal and Griffin

7 Mask Light Deposited Film Substrate Film deposition hotoresist hotoresist application Exposure Etch mask Development Etching Resist removal Basic lithography process which is central to today s chip fabrication. Lithographic process allows integration of multiple devices side by side on a wafer. SILICO VLSI TECHOLOGY by rentice Hall Fundamentals, ractice and Modeling Upper Saddle River, J. By lummer, Deal and Griffin

8 Well Well Schematic cross-section of a modern silicon IC. (Reprinted with permission of Integrated Circuit Engineering.) Actual cross-section of a modern microprocessor chip. ote the multiple levels of metal and planarization. SILICO VLSI TECHOLOGY by rentice Hall Fundamentals, ractice and Modeling Upper Saddle River, J. By lummer, Deal and Griffin

9 Computer Simulation Tools (TCAD) Most of the basic technologies in silicon chip manufacturing can now be simulated. Simulation is now used for: Designing new processes and devices. Exploring the limits of semiconductor devices and technology (R&D). Centering manufacturing processes. Solving manufacturing problems (what-if?) Simulation of an advanced local oxidation process. Simulation of photoresist exposure. SILICO VLSI TECHOLOGY by rentice Hall Fundamentals, ractice and Modeling Upper Saddle River, J. By lummer, Deal and Griffin

10 Summary of Key Ideas ICs are widely regarded as one of the key components of the information age. Basic inventions between 1945 and 1970 laid the foundation for today's silicon industry. For more than 30 years, "Moore's Law" (a doubling of chip complexity every 2-3 years) has held true. CMOS has become the dominant circuit technology because of its low DC power consumption, high performance and flexible design options. Future projections suggest these trends will continue through at least 2010 and likely beyond. Computer simulation tools have been widely used for device, circuit and system design for many years. ew tools are now being used for technology design as well. Chapter 1 also contains some review information on semiconductor materials and basic semiconductor devices for students who have not studied this material or who wish to review these areas. These topics will be useful in later chapters of the text. SILICO VLSI TECHOLOGY by rentice Hall Fundamentals, ractice and Modeling Upper Saddle River, J. By lummer, Deal and Griffin