Vertical Nanowire InGaAs MOSFETs Fabricated by a Top-down Approach

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1 Vertical Nanowire InGaAs MOSFETs Fabricated by a Top-down Approach Xin Zhao, Jianqiang Lin, Christopher Heidelberger, Eugene A. Fitzgerald and Jesús A. del Alamo Microsystems Technology Laboratories, MIT December 11, 2013 Sponsors: NSF Award # (E3S STC) Fabrication: MTL, SEBL at MIT

2 Outline Motivation Device technology Device electrical characteristics Conclusions 2

3 3 Motivation Superior electron transport properties of InGaAs material system high mobility and electron velocity del Alamo, Nature 2011

4 Gate-all-around (GAA) nanowire MOSFETs Kuhn, TED 2012 Nanowire MOSFET provides ultimate scalability 4

5 Vertical channel MOSFETs Vertical nanowire decouples footprint scaling and gate length scaling high density Liu, DRC 2012 Use of vertical FETs saves 40% of total chip area 5

6 Bottom-up approach Impressive devices via bottom-up techniques demonstrated Complicated epitaxial growth or Au seed particles required Tanaka, APEX 2010 Tomioka, Nature 2012 Persson, DRC 2012 Top-down approach worth investigating! 6

7 Goal: vertical nanowire InGaAs MOSFETs fabricated via top-down approach Starting heterostructure: n+ InGaAs, 70 nm i InGaAs, 80 nm n+ InGaAs, 300 nm n+: Si doping Mo/Ti/Au n+ SOG W i Al 2 O 3 n+ InGaAs Key elements: Top-down approach based on RIE Single nanowire MOSFETs 7

8 Tomioka, Nature 2012 Persson, DRC 2012 InGaAs Adhesion layer Starting substrate n+ i n+ HSQ n+ i n+ Process flow Sputtered W ALD-Al 2 O 3 1 st SOG 2 nd SOG Mo/Ti/Au 8

9 Key enabling technology: RIE by BCl 3 /SiCl 4 /Ar Chemistry 20 nm Sub-20 nm resolution Aspect ratio > 10 Smooth sidewall and surface BCl 3 /SiCl 4 /Ar RIE chemistry used for III-V optical devices, never used for nm-scale features 9

10 Critical parameter: Substrate temperature during RIE T etch rate, surface roughness, sidewall verticality 10

11 Nanowire RIE followed by digital etch Digital etch: self-limiting O 2 plasma oxidation + H 2 SO 4 oxide removal before after 10 cycles Lin, IEDM 2012 Shrinks NW diameter by 2 nm per cycle Unchanged shape Reduced roughness 11

12 Planarization and etch back W ALD-Al 2 O 3 After 1 st planarization 1 st SOG 40 nm SOG After 2 nd planarization 50 nm W gate metal 2 nd SOG 50 nm 30 nm 12

13 NW-MOSFET I-V characteristics D= 30 nm I d (µa/µm) V gs =-0.6 V to 0.8 V in 0.1 V step R on =759 Ω.µm (at V gs =1 V) V ds (V) I d (µa/µm) g m, pk (V ds =0.5 V) =280 µs/µm V ds =0.5 V V gs (V) g m (µs/µm) Single nanowire MOSFET: D= 30 nm L ch = 80 nm 4.5 nm Al 2 O 3 (EOT = 2.2 nm) At V DS =0.5 V (normalized by periphery): g m,pk =280 μs/μm R on =759 Ω.μm 13

14 D=30 nm InGaAs NW-MOSFETs 10-4 V ds =0.5 V I g < 10-9 A/µm I d (A/µm) V ds =0.05 V DIBL=195 mv/v S=145 mv/dec, V ds =0.05 V S= mv/dec, V ds =0.5 V V gs (V) 14

15 D=50 nm InGaAs NW-MOSFET I d (µa/µm) V gs =-0.6 V to 0.8 V in 0.1 V step R on =310 Ω.µm (at V gs =1 V) V ds (V) I d (µa/µm) g m, pk (V ds =0.5 V) 600 =730 µs/µm V ds =0.5 V V gs (V) g m (µs/µm) At V ds =0.5 V: g m,pk =730 μs/μm R on =310 Ω.μm 15

16 D=50 nm InGaAs NW-MOSFETs 10-3 V ds =0.5 V I g < A/µm I d (A/µm) V ds =0.05 V DIBL=360 mv/v S=210 mv/dec, V ds =0.05 V S=305 mv/dec, V ds =0.5 V V gs (V) 16

17 S (mv/dec) g m (µs/µm) Impact of nanowire diameter V ds =0.5 V V ds =0.05 V Diameter (nm) V ds =0.5 V Diameter (nm) DIBL (mv/v) R on (Ω.µm) V gs =1 V Diameter (nm) Diameter (nm) D S, DIBL, g m, R on Error bars indicate distribution of ~10 devices 17

18 Impact of digital etch I d (A/µm) Single nanowire MOSFET: D= 40 nm (final diameter) V ds =0.5 V digital etch no digital etch V gs (V) V ds =0.05 V Digital etch S, g m, I g Better sidewall interface R on and DIBL unchanged g m (µs/µm) digital etch no digital etch V ds =0.5 V digital etch V gs (V) no digital etch I g (A/cm 2 )10-3 Vds=1 V V gs (V) 18

19 Benchmarking against bottom-up vertical InGaAs NW-MOSFETs Persson, EDL 2012 Tomioka, Nature 2012 g m,pk (µs/µm) Tanaka, APEX 10 Tomioka, IEDM 11 Tomioka, Nature 12 Persson, DRC 12 Persson, EDL 10 This work (Top down) This work V ds =0.5 V S(mV/dec) Bottom up Persson, DRC 2012 Tanaka, APEX 2010 Fundamental trade-off between transport and short-channel effects Top-down NW-MOSFETs as good as bottom up devices 19

20 Conclusions First demonstration of top-down III-V GAA NW- MOSFET with vertical channel Novel III-V RIE process with sub-20 nm resolution 30 nm diameter NW MOSFET achieved Digital etch improves subthreshold and transport characteristics Device performance matches that of best bottom-up vertical NW III-V MOSFETs 20

21 Acknowledgement NSF E3S Fabrication facility at MIT labs: MTL, SEBL MIT colleagues: T. Yu, L. Guo, W. Chern, A. Vardi, L. Xia, D. Antoniadis, J. Hoyt, D. Jin, A. Guo, S. Warnock, W. Lu, Y. Wu, J. Teherani E3S colleagues: A. Lakhani, S. Agarwal, M. Eggleston, E. Yablonovitch, M. Wu 21

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