Supporting Information

Transcription

1 Supporting Information Fabrication and Transfer of Flexible Few-Layers MoS 2 Thin Film Transistors to any arbitrary substrate Giovanni A. Salvatore 1, *, Niko Münzenrieder 1, Clément Barraud 2, Luisa Petti 1, Christoph Zysset 1, Lars Büthe 1, Klaus Ensslin 2 and Gerhard Tröster 1 1 Electronics Laboratory, ETZ Gloriastrasse 35, Swiss Federal Institute of Technology, Zürich, 8092, Switzerland 2 Nanophysics Laboratory, HPF Schafmattstrasse 16, Swiss Federal Institute of Technology, Zürich, 8093, Switzerland. *giovanni.salvatore@ife.ee.ethz.ch

2 Transfer technique Figure S1: PMMA membrane transferred on a 50µm thick polymide foil (in orange). Usually no winkles are visible between the membrane and the substrate, moreover the annealing step at 70 C for 10minutes improves the adhesion and evaporates the remaining water. Mobility extraction The mobility extraction is performed through the I D / g m method 2. 5x10-4 4x10-4 I D /g 1/2 m 3x10-4 2x10-4 µ=19 cm 2 /Vs 1x Gate-Source Voltage, V GS Figure S2: Mobility extraction through the Ghibaudo s method.

3 Source-Drain contacts Source and drain are formed by 100nm Au layer. Drain current Vs Drain voltage for low values shows a linear behavior as already reported Drain Current, I D (µa/µm) 0.0 V GS =-2V,-1V,0V,1V,2V Drain-Source Voltage, V DS Figure S3: I D -V D for low voltage values. The curves refer to V GS from -2V to 2V with a 1V step.

4 Transconductance, g DS and intrinsic gain g m /g DS Transistor transconductance, g m = I D / V GS, and output resistance, 1/g DS == I D / V DS, are two important parameter to evaluate the device performance. Here we plotted such parameters as function of the gate voltage. The plot refers to the device of Figure /g DS = R OUT (MΩ) g m /g DS Gate-Source Voltage, V GS Transconductance, g m (µs) Gate-Source Voltage, V GS 4 Figure S4: transconductance and output resistance of the device in Figure 3. The inset shows the intrinsic gain defined as g m /g DS. The calculation has been done for the saturation regime. Interface residuals and interface charges density extraction The authors didn t perform any measurements in vacuum but they do not expect a much different behavior. Annealing step could be beneficial and some experiments are ongoing. From the subthreshold swing value and through simple assumptions and calculation, interface charge can be calculated.

5 In fact, the subthreshold swing can be written as: 3, (1) This model is usually adopted for Silicon on Insulator 3 thin film transistor which is indeed similar to our structure. Assuming an ideal interface (C IT =0) and a perfect gate-channel coupling (C S /C OX 0), which is the case in ultra-thin body transistors, the subthreshold swing reach the ideal value of 60mV/dec. Assuming such values as reference the term C IT /C OX can be calculated from equation (1). Our 250mV/dec implies a C IT /C OX of about 3 and hence a C IT of 10.2 * 10-7 F/cm 2 (in the case of 25nm of Al 2 O 3 with a dielectric constant of 9.5). This can give a D IT (density of charge=d IT =Q IT /q) of 6.4*10 12 /cm 2 assuming a 1V subthreshol region. CMOS transistors could have D IT as low as /cm 2. The same result can be achieved by multiplying the difference of the threshold voltage by the oxide capacitance ( V TH *C OX ).

6 Bending tests Measurements under bent conditions are performed by bending the devices around a metallic rod with 10 and 5mm radii. A custom built bending machine has been used for the bending cycles. The device are bent down to 10mm radii during the cycling. a b Figure S5: (a) Devices bent around a metallic rod used for the measurement. The TFTs are contacted directly with probe tips. The devices are bent in such a way the strain is parallel to the channel of the TFTs. (b) Custom built machine to perform multiple and consecutive bending cycles.

7 Output characteristics for bending test a Drain Current, I D (µa/µm) flat 10mm bending radius 5mm bending radius Drain-Source Voltage, V DS b Drain Current, I D (µa/µm) flat after 10 bending cycles Drain-Source Voltage, V DS Figure S6: (a) Output characteristics of a device (same TFT than in figure 3 and 4) when bent to 5 and 10mm. (b) Device output characteristic after 10 consecutive bending cycles at 10mm as minimum bending radius. References 1. Radisavljevic B.; Radenovic A.; Brivio J.; Giacometti V.; Kis A. Single-Layer MoS2 Transistors Nature Nanotech. 2011, 6, Ghibaudo, G. New Method for the Extraction of MOSFET Parameters Electron. Lett. 1988, 24, Colinge, J.-P. Subthreshold Slope of Thin-Film SOI MOSFET's Elec. Dev. Lett., IEEE 1986, 7, Van Overstraeten, R. J.; Declerck, G. J.; Muls, P. A. Theory of the MOS Transistor in Weak Inversion-New Method to Determine the Number of Surface States Trans. Elec. Dev., IEEE 1975, 22,