SOI technology platforms for 5G: Opportunities of collaboration

Size: px
Start display at page:

Download "SOI technology platforms for 5G: Opportunities of collaboration"

Transcription

1 SOI technology platforms for 5G: Opportunities of collaboration Dr. Ionut RADU Director, R&D SOITEC MOS AK workshop, Silicon Valley December 6th, 2017

2 Sourcing value from substrate Robert E. White ISBN-13:

3 Agenda 1 Material innovation supporting semiconductor industry 2 RF SOI technology 3 FD SOI technology 4 SOI mix signal platforms for 5G 4 Outlook 3

4 5G era 4

5 Challenges Opportunities for semiconductor innovation 5

6 Material at the heart of semiconductor innovation 6

7 More Moore / More Than Moore More functionalities (Sensing, communication, ) INTEGRATION! Computing, Performance, Power Courtesy of Johann Knechtel, ICCD

8 Material stacking : different configurations Crystal on Crystal (compatible lattice) Amorphous on Amorphous Crystal on Crystal (not compatible lattice) Crystal on Amorphous EPITAXY DEPOSITION (XX-CVD) IMPLANT Smart-Cut TM thin / highly uniform layers 8

9 Revolutionary Smart Cut Industrial maturity (25+ years) Uniformity and layer integrity Donor refreshing Flexibility of material integration 9

10 Material Options Top Si Smart Cut TM versatility Silicon On Insulator Thickness Capabilities Silicon On Sapphire Smart Power SOI TM Piezo On Insulator RF-SOI Photonics SOI PD-SOI InGaN On Sapphire Top Silicon FD-SOI Buried Oxide Base Silicon BOX InP On GaAs 10

11 Engineered substrates supporting our daily drivers 11

12 Agenda 1 Material innovation supporting semiconductor industry 2 RF SOI technology 3 FD SOI technology 4 SOI mix signal platforms for 5G 4 Outlook 12

13 RF-SOI For high efficient mobile communication Power Mono-crystal Top Material Buried Oxide Trap Rich Layer High Resistive Base High resistivity base wafer combined with low mobility trap rich layer just beneath the BOX Low insertion loss (quasi lossless substrate) Performance Cost Reduced crosstalk compared to bulk High linearity compatible with 4G standards Lower cost than MEMS or BSOS based solutions 13

14 RF-SOI - Multiple design platforms for Front End Modules Addressing current needs and new challenges > 10 foundries in HVM mode RF-SOI 45nm RF-SOI 65nm RF-SOI 90nm RF-SOI 0.13um RF-SOI 0.18um Switch DAC PLL + mmw Antenna Tuner Mixers < 6Ghz ADC LNA RF-SOI 0.25um PA Digital 14

15 Enhanced Signal Integrity SOI - esi Trap Rich layer freezes the highly conductive layer at BOX Handle interface Fixed charges Mono-crystal Top Silicon SiO 2 (BOX) Trap rich layer Mobile & Interface trapped charges High Resistivity SI Base 15

16 Substrate s direct impact on die performance esi vs. HR-SOI performance RF Loss Crosstalk Linearity Thermal Conductivity (reducing BOX thickness) High Q Passives 145 nm 25 nm 10 nm Die Size HR-SOI esi 16

17 Agenda 1 Material innovation supporting semiconductor industry 2 RF SOI technology 3 FD SOI technology 4 SOI mix signal platforms for 5G 4 Outlook 17

18 FD-SOI For power efficient & flexible digital computing with easy Analog/RF integration Ultra-thin top silicon & box enabling fully-depleted transistor operation Mono-crystal Top Material 18 Thin Buried Oxide Base (Si) Power Junction capacitance removal Body Bias enabling ULV operation Performance Cost Sub 20nm device scaling Very low mismatch On demand performance through body bias mmwave compatible RF device Immunity to high energy particules Superior analog device behavior compared to bulk Process, temperature & ageing compensation through body bias Lower manufacturing cost for foundry than bulk Lower NRE than FinFET

19 Back-Biasing principle Concept: Bias applied to tune body potential. Body Factor: Efficiency of V T tuning. Technique similar to Bulk AVS FDSOI: Wider range and better efficiency. Effect V T tunning (several decades of I OFF ). Same transistor can give high I on (low V T ) and Low I OFF (high V T ). Back Bias High I ON V T shift Low I OFF P. Flatresse et al. S3S Conference Short Course, 2014 V dd 19

20 SS FF IDDQ Leakage IDDQ EWS/Room Neutron-SER in FT/Mb Very unique features same technology platform mmwave RF-CMOS Ultra Low Voltage Process compensation through body bias Immunity to radiations Leakage limit Untrimmed Performace Boost Leakage spread reduction Trimmed 28nm FD-SOI Source: GF, GTC2017 Source: Sugii,Low Power El. Appl Frequency Source: P. Flatresse, ST, ICICDT17 ST Vendor A ST Vendor A ST ST 65nm 45nm 45nm 28nm 28nm 28nm Bulk Bulk Bulk Bulk Bulk FD-SOI Source: ST, Shanghai FDSOI forum, 2015 Best CMOS mmwave with similar performance to SiGe radios Operation at minimum energy point (<0.4V) 4X less process spread +15% frequency boost 20x Soft Error Rate improvement vs. bulk 20

21 Channel and Back-Gate oxide within starting substrate Ultra-Thin Top Silicon Layer Ultra-Thin Buried Oxide Base Silicon Substrate characteristics Thickness Uniformity Micro-roughness Macro-roughness Electrical properties Defectivity Metal contamination Thickness Uniformity Parasitics charges Integrity (Breakdown voltage) Geometry Bulk Micro Defects Metal contamination Impact on device Electrostatics Variability Mobility Yield Electrostatics Back gate control Variability Reliability Yield + variability All these characteristics are key to control in FD-SOI 21

22 iavt (mv.µm) Material vs device characteristics (supported by TCAD models) Top Si : Thin and uniform top layer is key to maintain good electrostatics and variability: BOX : Thin BOX is key to maintain good electrostatics and body factor: NMOS wafer_1 Tsi=10nm wafer_9 Tsi=12nm wafer_17 Tsi=15nm S (µm²) 10nm 12nm 15nm 22

23 Thickness control ± 1 Atomic Layer! Silicon thickness uniformity is guaranteed to within just a few atomic layers: +5Å Target -5Å Soitec FD-SOI wafer ±5Å ±0.9mm 23

24 iavt (mv.µm) Many different spatial frequencies to consider in FD-SOI SOI Box Handle wafer Wafer to Wafer Thickness Uniformity Within Wafer Within Wafer 10-6 Thickness Uniformity 10-2 Macro roughness 1 Within Wafer Micro roughness µm High Macro Roughness 10 8 Low Macro Roughness S (µm²) Macro-roughness is one of the key parameters for FD-SOI

25 Efficient collaboration with equipment vendors Example of FD-SOI roughness management Enhanced smoothing in high temperature batch anneal technology F.De Crecy CEA/LETI Simulation of silicon smoothing under high temp anneal Unique chip scale thickness measurement developed with HSEB HSEB Baldur tool FD-SOI Local Thickness Variability Within Wafer Uniformity DRM 6s (A) < 3.0 < 3.5 < 4.0 < 4.5 < 5.0 < 5.5 < 6.0 < 6.5 < 7.0 > 7.0 Tool customized with new deposit management for SOI manufacturing New tool redesign ongoing for enhanced flow managment to achieve ultimate FD-SOI roughness & uniformity Collaboration on Differential Reflective Metrology development Full map thickness measurement a critical parameter for FD- SOI 25

26 FD-SOI thickness performance 26

27 FD-SOI : 15nm HVM box scaling demonstrated 27

28 A multi-nodes FD-SOI Product Roadmap Target node 65FD 28FD 22FD 12FD Beyond 12FD Box thick. 15nm 25nm 20nm 15 20nm 20nm FD-SOI substrate Top Si unif Top Si thick. Top Si Mob. ± 1.0 nm 30 nm Si unstrained ± 0.5 nm 12 nm Si unstrained ± 0.5 nm 12 nm Si unstrained ± 0.4 nm 12 nm Si unstrained tbd Pending device Si / SiGe Strained / relaxed Industrial status Prod. Prod. Prod. Dev. R&D 28

29 FD-SOI Multiple Foundry Offering In development FDS 18nm FDX 12nm RF emram FDX 22nm RF emram In production SOTB 65nm FDS 28nm RF emram 29

30 Accelerating FD-SOI Adoption Consumer: a game changer technology for better battery life Automotive : best power efficiency allowing simpler integration and enhanced reliability FD-SOI cuts standard GPS power consumption by 5 to 10 times 30 i.mx reference platform by NXP FD-SOI - Reference technology for ADAS level 3 applications Next generation e- Cockpit solution with full management of car infotainment

31 Agenda 1 Material innovation supporting semiconductor industry 2 RF SOI technology 3 FD SOI technology 4 SOI mix signal platforms for 5G 4 Outlook 31

32 SOI mixed signal platforms for 4G & 5G Mixed signal design & integration options Lower Power Higher Frequency Signal Integrity No junction capacitance Back Bias Ultra low VDD Short Channels Low Device Parasitics Forward Body Bias Low transmission loss High isolation Low harmonics FD-SOI Wide range of digital app. Ultra Low Power IoT Transceivers Low Power analog 5G Front End Module 5G transceivers Radar mmwave (77Ghz) PD-SOI / HR 5G Front End Module RF-SOI / RFeSI 3/4G Front End Module Antenna Switch Antenna Tuner Low Noise Amplifier Power Amplifier 32

33 FD-SOI Technology for 5G mmw Source : GlobalFoundries, Practical MMWave 5G Solutions, J. Jensen, CICC 2017 FD-SOI made with regular FD-SOI 22nm wafer Integration of full Front End Module and transceiver Under evaluation by fabless 33

34 Take-Aways Engineered substrate brings value (i.e. PPAC) to device and electronic circuits SOI substrates are enabling functionalities integration => paradigm shift Smart Cut enables heterogeneous material integration meeting 5G applications requirements Close collaboration and partnership starting at early development phases between technology developers and device and circuit modeling is mandatory to design the 5G products 34

35 Broad innovation: Multi-dimensional, multi-partner Innovation platforms (i.e. 5G) Systems ICs Substrate Device System co-optimization from early R&D Smart Substrates 35

How material engineering contributes to delivering innovation in the hyper connected world

How material engineering contributes to delivering innovation in the hyper connected world How material engineering contributes to delivering innovation in the hyper connected world Paul BOUDRE, Soitec CEO Leti Innovation Days - July 2018 Grenoble, France We live in a world of data In perpetual

More information

Engineered substrates - at the heart of 4G/5G FEM evolution

Engineered substrates - at the heart of 4G/5G FEM evolution Engineered substrates - at the heart of 4G/5G FEM evolution Bernard ASPAR EVP Communication & Power Business Unit, Soitec SOI Consortium, Shanghai, September 2018 1 FEM market 2 RF-SOI 3 POI RF FEM market

More information

GLOBALFOUNDRIES RF Business Unit. November 2015

GLOBALFOUNDRIES RF Business Unit. November 2015 GLOBALFOUNDRIES RF Business Unit November 2015 RF Business Unit outlook is strong Standards evolution & consumer desires creating greater demand for devices that can support data rich content, and the

More information

FinFET vs. FD-SOI Key Advantages & Disadvantages

FinFET vs. FD-SOI Key Advantages & Disadvantages FinFET vs. FD-SOI Key Advantages & Disadvantages Amiad Conley Technical Marketing Manager Process Diagnostics & Control, Applied Materials ChipEx-2014, Apr 2014 1 Moore s Law The number of transistors

More information

Silicon on Insulator (SOI) Spring 2018 EE 532 Tao Chen

Silicon on Insulator (SOI) Spring 2018 EE 532 Tao Chen Silicon on Insulator (SOI) Spring 2018 EE 532 Tao Chen What is Silicon on Insulator (SOI)? SOI silicon on insulator, refers to placing a thin layer of silicon on top of an insulator such as SiO2. The devices

More information

FD-SOI Technology. Bich-Yen Nguyen Soitec

FD-SOI Technology. Bich-Yen Nguyen Soitec FD-SOI Technology Bich-Yen Nguyen Soitec Agenda 1 FD-SOI technology overview 2 Markets, foundries offers & ecosystems 3 FD-SOI material & roadmap 4 Summary 10/10/2017 2 SOITEC Confidential FD-SOI technology

More information

Sub-micron technology IC fabrication process trends SOI technology. Development of CMOS technology. Technology problems due to scaling

Sub-micron technology IC fabrication process trends SOI technology. Development of CMOS technology. Technology problems due to scaling Goodbye Microelectronics Welcome Nanoelectronics Sub-micron technology IC fabrication process trends SOI technology SiGe Tranzistor in 50nm process Virus The thickness of gate oxide= 1.2 nm!!! Today we

More information

Session 3: Solid State Devices. Silicon on Insulator

Session 3: Solid State Devices. Silicon on Insulator Session 3: Solid State Devices Silicon on Insulator 1 Outline A B C D E F G H I J 2 Outline Ref: Taurand Ning 3 SOI Technology SOl materials: SIMOX, BESOl, and Smart Cut SIMOX : Synthesis by IMplanted

More information

Semiconductor Devices

Semiconductor Devices Semiconductor Devices - 2014 Lecture Course Part of SS Module PY4P03 Dr. P. Stamenov School of Physics and CRANN, Trinity College, Dublin 2, Ireland Hilary Term, TCD 3 th of Feb 14 MOSFET Unmodified Channel

More information

ITRS: RF and Analog/Mixed- Signal Technologies for Wireless Communications. Nick Krajewski CMPE /16/2005

ITRS: RF and Analog/Mixed- Signal Technologies for Wireless Communications. Nick Krajewski CMPE /16/2005 ITRS: RF and Analog/Mixed- Signal Technologies for Wireless Communications Nick Krajewski CMPE 640 11/16/2005 Introduction 4 Working Groups within Wireless Analog and Mixed Signal (0.8 10 GHz) (Covered

More information

FDSOI for Low Power System on Chip. M.HAOND STMicroelectronics, Crolles, France

FDSOI for Low Power System on Chip. M.HAOND STMicroelectronics, Crolles, France FDSOI for Low Power System on Chip M.HAOND STMicroelectronics, Crolles, France OUTLINE Introduction : Motivations for FDSOI FDSOI Presentation & Short Channel control MOS VT Construction Performance Analysis

More information

Lecture #29. Moore s Law

Lecture #29. Moore s Law Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday

More information

LSI ON GLASS SUBSTRATES

LSI ON GLASS SUBSTRATES LSI ON GLASS SUBSTRATES OUTLINE Introduction: Why System on Glass? MOSFET Technology Low-Temperature Poly-Si TFT Technology System-on-Glass Technology Issues Conclusion System on Glass CPU SRAM DRAM EEPROM

More information

Alternatives to standard MOSFETs. What problems are we really trying to solve?

Alternatives to standard MOSFETs. What problems are we really trying to solve? Alternatives to standard MOSFETs A number of alternative FET schemes have been proposed, with an eye toward scaling up to the 10 nm node. Modifications to the standard MOSFET include: Silicon-in-insulator

More information

Signal Integrity Design of TSV-Based 3D IC

Signal Integrity Design of TSV-Based 3D IC Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr 1 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues

More information

IOLTS th IEEE International On-Line Testing Symposium

IOLTS th IEEE International On-Line Testing Symposium IOLTS 2018 24th IEEE International On-Line Testing Symposium Exp. comparison and analysis of the sensitivity to laser fault injection of CMOS FD-SOI and CMOS bulk technologies J.M. Dutertre 1, V. Beroulle

More information

Research Needs for Device Sciences Modeling and Simulation (May 6, 2005)

Research Needs for Device Sciences Modeling and Simulation (May 6, 2005) Research Needs for Device Sciences Modeling and Simulation (May 6, 2005) SRC Device Sciences 2005 Modeling and Simulation Task Force Contributing organizations: Axcelis, Freescale, IBM, Intel, LSI, SRC,

More information

RF and SOI Technologies for 5G

RF and SOI Technologies for 5G RF and SOI Technologies for 5G Kirk Ouellette VP, World Wide Strategy Development and Strategic Marketing RFSOI conference, SOI Consortium, Shanghai September 19, 2018 Agenda 2 Introduction 5G Disruption

More information

Simulation of High Resistivity (CMOS) Pixels

Simulation of High Resistivity (CMOS) Pixels Simulation of High Resistivity (CMOS) Pixels Stefan Lauxtermann, Kadri Vural Sensor Creations Inc. AIDA-2020 CMOS Simulation Workshop May 13 th 2016 OUTLINE 1. Definition of High Resistivity Pixel Also

More information

Intel s High-k/Metal Gate Announcement. November 4th, 2003

Intel s High-k/Metal Gate Announcement. November 4th, 2003 Intel s High-k/Metal Gate Announcement November 4th, 2003 1 What are we announcing? Intel has made significant progress in future transistor materials Two key parts of this new transistor are: The gate

More information

Wafer-scale 3D integration of silicon-on-insulator RF amplifiers

Wafer-scale 3D integration of silicon-on-insulator RF amplifiers Wafer-scale integration of silicon-on-insulator RF amplifiers The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation As Published

More information

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs 1 CMOS Digital Integrated Circuits 3 rd Edition Categories of Materials Materials can be categorized into three main groups regarding their

More information

ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations

ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations Workshop on Frontiers of Extreme Computing Santa Cruz, CA October 24, 2005 ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations Peter M. Zeitzoff Outline Introduction MOSFET scaling and

More information

Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018

Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 ECE 658 Sp 2018 Semiconductor Materials and Device Characterizations OUTLINE Background FinFET Future Roadmap Keeping up w/ Moore s Law

More information

HOW TO CONTINUE COST SCALING. Hans Lebon

HOW TO CONTINUE COST SCALING. Hans Lebon HOW TO CONTINUE COST SCALING Hans Lebon OUTLINE Scaling & Scaling Challenges Imec Technology Roadmap Wafer size scaling : 450 mm 2 COST SCALING IMPROVED PERFORMANCE 3 GLOBAL TRAFFIC FORECAST Cloud Traffic

More information

Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007

Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 33-1 Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007 Contents: 1. MOSFET scaling

More information

FD-SOI FOR RF IC DESIGN. SITRI LETI Workshop Mercier Eric 08 september 2016

FD-SOI FOR RF IC DESIGN. SITRI LETI Workshop Mercier Eric 08 september 2016 FD-SOI FOR RF IC DESIGN SITRI LETI Workshop Mercier Eric 08 september 2016 UTBB 28 nm FD-SOI : RF DIRECT BENEFITS (1/2) 3 back-end options available Routing possible on the AluCap level no restriction

More information

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI Lecture: Integration of silicon photonics with electronics Prepared by Jean-Marc FEDELI CEA-LETI Context The goal is to give optical functionalities to electronics integrated circuit (EIC) The objectives

More information

CMP for More Than Moore

CMP for More Than Moore 2009 Levitronix Conference on CMP Gerfried Zwicker Fraunhofer Institute for Silicon Technology ISIT Itzehoe, Germany gerfried.zwicker@isit.fraunhofer.de Contents Moore s Law and More Than Moore Comparison:

More information

Laser attacks on integrated circuits: from CMOS to FD-SOI

Laser attacks on integrated circuits: from CMOS to FD-SOI DTIS 2014 9 th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Laser attacks on integrated circuits: from CMOS to FD-SOI J.-M. Dutertre 1, S. De Castro 1, A. Sarafianos

More information

International Journal of Scientific & Engineering Research, Volume 6, Issue 2, February-2015 ISSN

International Journal of Scientific & Engineering Research, Volume 6, Issue 2, February-2015 ISSN Performance Evaluation and Comparison of Ultra-thin Bulk (UTB), Partially Depleted and Fully Depleted SOI MOSFET using Silvaco TCAD Tool Seema Verma1, Pooja Srivastava2, Juhi Dave3, Mukta Jain4, Priya

More information

IFSIN. WEB PAGE Fall ://weble.upc.es/ifsin/

IFSIN. WEB PAGE   Fall ://weble.upc.es/ifsin/ IFSIN IMPLEMENTACIÓ FÍSICA DE SISTEMES INTEGRATS NANOMÈTRICS IMPLEMENTACIÓN N FÍSICA F DE SISTEMAS INTEGRADOS NANOMÉTRICOS PHYSICAL IMPLEMENTATION OF NANOMETER INTEGRATED SYSTEMS Fall 2008 Prof. Xavier

More information

Design cycle for MEMS

Design cycle for MEMS Design cycle for MEMS Design cycle for ICs IC Process Selection nmos CMOS BiCMOS ECL for logic for I/O and driver circuit for critical high speed parts of the system The Real Estate of a Wafer MOS Transistor

More information

Mostafa Emam Tuesday 14 November

Mostafa Emam Tuesday 14 November Mostafa Emam mostafa.emam@incize.com Tuesday 14 November 2017 http://www.linkedin.com/company/incize Since 2014 Louvain-la-Neuve, Belgium MEASUREMENT, CHARACTERIZATION & MODELING SERVICES FOR SI & III-V

More information

Final Exam Topics. IC Technology Advancement. Microelectronics Technology in the 21 st Century. Intel s 90 nm CMOS Technology. 14 nm CMOS Transistors

Final Exam Topics. IC Technology Advancement. Microelectronics Technology in the 21 st Century. Intel s 90 nm CMOS Technology. 14 nm CMOS Transistors ANNOUNCEMENTS Final Exam: When: Wednesday 12/10 12:30-3:30PM Where: 10 Evans (last names beginning A-R) 60 Evans (last names beginning S-Z) Comprehensive coverage of course material Closed book; 3 sheets

More information

Gallium nitride (GaN)

Gallium nitride (GaN) 80 Technology focus: GaN power electronics Vertical, CMOS and dual-gate approaches to gallium nitride power electronics US research company HRL Laboratories has published a number of papers concerning

More information

Plan Optik AG. Plan Optik AG PRODUCT CATALOGUE

Plan Optik AG. Plan Optik AG PRODUCT CATALOGUE Plan Optik AG Plan Optik AG PRODUCT CATALOGUE 2 In order to service the high demand of wafers more quickly, Plan Optik provides off the shelf products in sizes from 2 up to 300mm diameter. Therefore Plan

More information

First Results of 0.15μm CMOS SOI Pixel Detector

First Results of 0.15μm CMOS SOI Pixel Detector First Results of 0.15μm CMOS SOI Pixel Detector International Symposium on Detector Development SLAC, CA, April 5, 2006 KEK Detector Technology Project : [SOIPIX Group] Yasuo Arai (KEK) Y. Arai Y. Ikegami

More information

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI 1 Integrated diodes pn junctions of transistor structures can be used as integrated diodes. The choice of the junction is limited by the considerations of switching speed and breakdown voltage. The forward

More information

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 LECTURE 020 ECE 4430 REVIEW II (READING: GHLM - Chap. 2) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught

More information

Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics

Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1 Topics What is semiconductor Basic semiconductor devices Basics of IC processing CMOS technologies 2006/9/27 2 1 What is Semiconductor

More information

420 Intro to VLSI Design

420 Intro to VLSI Design Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem

More information

Newer process technology (since 1999) includes :

Newer process technology (since 1999) includes : Newer process technology (since 1999) includes : copper metalization hi-k dielectrics for gate insulators si on insulator strained silicon lo-k dielectrics for interconnects Immersion lithography for masks

More information

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 LECTURE 020 ECE 4430 REVIEW II (READING: GHLM - Chap. 2) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught

More information

A Bandgap Voltage Reference Circuit Design In 0.18um Cmos Process

A Bandgap Voltage Reference Circuit Design In 0.18um Cmos Process A Bandgap Voltage Reference Circuit Design In 0.18um Cmos Process It consists of a threshold voltage extractor circuit and a proportional to The behavior of the circuit is analytically described, a design

More information

Fundamentals of CMOS Image Sensors

Fundamentals of CMOS Image Sensors CHAPTER 2 Fundamentals of CMOS Image Sensors Mixed-Signal IC Design for Image Sensor 2-1 Outline Photoelectric Effect Photodetectors CMOS Image Sensor(CIS) Array Architecture CIS Peripherals Design Considerations

More information

Parameter Optimization Of GAA Nano Wire FET Using Taguchi Method

Parameter Optimization Of GAA Nano Wire FET Using Taguchi Method Parameter Optimization Of GAA Nano Wire FET Using Taguchi Method S.P. Venu Madhava Rao E.V.L.N Rangacharyulu K.Lal Kishore Professor, SNIST Professor, PSMCET Registrar, JNTUH Abstract As the process technology

More information

Gallium Nitride (GaN) Technology & Product Development

Gallium Nitride (GaN) Technology & Product Development Gallium Nitride (GaN) Technology & Product Development IEEE IMS / MTT-S 2012 Montreal, Canada GaN A New Enabling Technology Five times faster, higher frequency, faster on-chip logic Five times more power,

More information

Assoc. Prof. Dr. MONTREE SIRIPRUCHYANUN

Assoc. Prof. Dr. MONTREE SIRIPRUCHYANUN 1 Assoc. Prof. Dr. MONTREE SIRIPRUCHYANUN Dept. of Teacher Training in Electrical Engineering 1 King Mongkut s Institute of Technology North Bangkok 1929 Bulky, expensive and required high supply voltages.

More information

Low Transistor Variability The Key to Energy Efficient ICs

Low Transistor Variability The Key to Energy Efficient ICs Low Transistor Variability The Key to Energy Efficient ICs 2 nd Berkeley Symposium on Energy Efficient Electronic Systems 11/3/11 Robert Rogenmoser, PhD 1 BEES_roro_G_111103 Copyright 2011 SuVolta, Inc.

More information

Innovative ultra-broadband ubiquitous Wireless communications through terahertz transceivers ibrow

Innovative ultra-broadband ubiquitous Wireless communications through terahertz transceivers ibrow Project Overview Innovative ultra-broadband ubiquitous Wireless communications through terahertz transceivers ibrow Mar-2017 Presentation outline Project key facts Motivation Project objectives Project

More information

Chapter 3 Basics Semiconductor Devices and Processing

Chapter 3 Basics Semiconductor Devices and Processing Chapter 3 Basics Semiconductor Devices and Processing 1 Objectives Identify at least two semiconductor materials from the periodic table of elements List n-type and p-type dopants Describe a diode and

More information

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor

More information

Body-Biased Complementary Logic Implemented Using AlN Piezoelectric MEMS Switches

Body-Biased Complementary Logic Implemented Using AlN Piezoelectric MEMS Switches University of Pennsylvania From the SelectedWorks of Nipun Sinha 29 Body-Biased Complementary Logic Implemented Using AlN Piezoelectric MEMS Switches Nipun Sinha, University of Pennsylvania Timothy S.

More information

Radio-Frequency Circuits Integration Using CMOS SOI 0.25µm Technology

Radio-Frequency Circuits Integration Using CMOS SOI 0.25µm Technology Radio-Frequency Circuits Integration Using CMOS SOI.5µm Technology Frederic Hameau and Olivier Rozeau CEA/LETI - 7, rue des Martyrs -F-3854 GRENOBLE FRANCE cedex 9 frederic.hameau@cea.fr olivier.rozeau@cea.fr

More information

Reducing Transistor Variability For High Performance Low Power Chips

Reducing Transistor Variability For High Performance Low Power Chips Reducing Transistor Variability For High Performance Low Power Chips HOT Chips 24 Dr Robert Rogenmoser Senior Vice President Product Development & Engineering 1 HotChips 2012 Copyright 2011 SuVolta, Inc.

More information

Power Reduction in RF

Power Reduction in RF Power Reduction in RF SoC Architecture using MEMS Eric Mercier 1 RF domain overview Technologies Piezoelectric materials Acoustic systems Ferroelectric materials Meta materials Magnetic materials RF MEMS

More information

PERSPECTIVES FOR DISRUPTIVE 200MM/8-INCH GAN POWER DEVICE AND GAN-IC TECHNOLOGY DR. DENIS MARCON SR. BUSINESS DEVELOPMENT MANAGER

PERSPECTIVES FOR DISRUPTIVE 200MM/8-INCH GAN POWER DEVICE AND GAN-IC TECHNOLOGY DR. DENIS MARCON SR. BUSINESS DEVELOPMENT MANAGER PERSPECTIVES FOR DISRUPTIVE 200MM/8-INCH GAN POWER DEVICE AND GAN-IC TECHNOLOGY DR. DENIS MARCON SR. BUSINESS DEVELOPMENT MANAGER What I will show you today 200mm/8-inch GaN-on-Si e-mode/normally-off technology

More information

Monolithic Pixel Sensors in SOI technology R&D activities at LBNL

Monolithic Pixel Sensors in SOI technology R&D activities at LBNL Monolithic Pixel Sensors in SOI technology R&D activities at LBNL Lawrence Berkeley National Laboratory M. Battaglia, L. Glesener (UC Berkeley & LBNL), D. Bisello, P. Giubilato (LBNL & INFN Padova), P.

More information

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-

More information

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor

More information

Technology Advantages for Analog/RF & Mixed-Signal Designs

Technology Advantages for Analog/RF & Mixed-Signal Designs Technology Advantages for Analog/RF & Mixed-Signal Designs Andreia Cathelin STMicroelectronics, Crolles, France SOI Consortium Forum, Tokyo, January 21 st, 2016 Agenda 2 At a glance ST 28nm UTBB FD-SOI

More information

Semiconductor Process Reliability SVTW 2012 Esko Mikkola, Ph.D. & Andrew Levy

Semiconductor Process Reliability SVTW 2012 Esko Mikkola, Ph.D. & Andrew Levy Semiconductor Process Reliability SVTW 2012 Esko Mikkola, Ph.D. & Andrew Levy 1 IC Failure Modes Affecting Reliability Via/metallization failure mechanisms Electro migration Stress migration Transistor

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

In this lecture we will begin a new topic namely the Metal-Oxide-Semiconductor Field Effect Transistor.

In this lecture we will begin a new topic namely the Metal-Oxide-Semiconductor Field Effect Transistor. Solid State Devices Dr. S. Karmalkar Department of Electronics and Communication Engineering Indian Institute of Technology, Madras Lecture - 38 MOS Field Effect Transistor In this lecture we will begin

More information

45nm Bulk CMOS Within-Die Variations. Courtesy of C. Spanos (UC Berkeley) Lecture 11. Process-induced Variability I: Random

45nm Bulk CMOS Within-Die Variations. Courtesy of C. Spanos (UC Berkeley) Lecture 11. Process-induced Variability I: Random 45nm Bulk CMOS Within-Die Variations. Courtesy of C. Spanos (UC Berkeley) Lecture 11 Process-induced Variability I: Random Random Variability Sources and Characterization Comparisons of Different MOSFET

More information

FinFET-based Design for Robust Nanoscale SRAM

FinFET-based Design for Robust Nanoscale SRAM FinFET-based Design for Robust Nanoscale SRAM Prof. Tsu-Jae King Liu Dept. of Electrical Engineering and Computer Sciences University of California at Berkeley Acknowledgements Prof. Bora Nikoli Zheng

More information

Pushing Ultra-Low-Power Digital Circuits

Pushing Ultra-Low-Power Digital Circuits Pushing Ultra-Low-Power Digital Circuits into the Nanometer Era David Bol Microelectronics Laboratory Ph.D public defense December 16, 2008 Pushing Ultra-Low-Power Digital Circuits into the Nanometer Era

More information

Atomic-layer deposition of ultrathin gate dielectrics and Si new functional devices

Atomic-layer deposition of ultrathin gate dielectrics and Si new functional devices Atomic-layer deposition of ultrathin gate dielectrics and Si new functional devices Anri Nakajima Research Center for Nanodevices and Systems, Hiroshima University 1-4-2 Kagamiyama, Higashi-Hiroshima,

More information

Design and Performance Analysis of SOI and Conventional MOSFET based CMOS Inverter

Design and Performance Analysis of SOI and Conventional MOSFET based CMOS Inverter I J E E E C International Journal of Electrical, Electronics ISSN No. (Online): 2277-2626 and Computer Engineering 3(2): 138-143(2014) Design and Performance Analysis of SOI and Conventional MOSFET based

More information

MA4AGSW2. AlGaAs SP2T PIN Diode Switch. MA4AGSW2 Layout. Features. Description. Absolute Maximum Ratings TA = +25 C (Unless otherwise specified)

MA4AGSW2. AlGaAs SP2T PIN Diode Switch. MA4AGSW2 Layout. Features. Description. Absolute Maximum Ratings TA = +25 C (Unless otherwise specified) AlGaAs SP2T PIN Diode Switch Features Ultra Broad Bandwidth: 5 MHz to 5 GHz Functional bandwidth : 5 MHz to 7 GHz.7 db Insertion Loss, 33 db Isolation at 5 GHz Low Current consumption: -1 ma for Low Loss

More information

Hot Topics and Cool Ideas in Scaled CMOS Analog Design

Hot Topics and Cool Ideas in Scaled CMOS Analog Design Engineering Insights 2006 Hot Topics and Cool Ideas in Scaled CMOS Analog Design C. Patrick Yue ECE, UCSB October 27, 2006 Slide 1 Our Research Focus High-speed analog and RF circuits Device modeling,

More information

3D Integration Using Wafer-Level Packaging

3D Integration Using Wafer-Level Packaging 3D Integration Using Wafer-Level Packaging July 21, 2008 Patty Chang-Chien MMIC Array Receivers & Spectrographs Workshop Pasadena, CA Agenda Wafer-Level Packaging Technology Overview IRAD development on

More information

+1 (479)

+1 (479) Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable

More information

Innovative Technologies for RF & Power Applications

Innovative Technologies for RF & Power Applications Innovative Technologies for RF & Power Applications > Munich > Nov 14, 2017 1 Key Technologies Key Technologies Veeco Market Focus Advanced Packaging, MEMS & RF Lighting, Display & Power Electronics Lithography

More information

Electrical Characterization of a Second-gate in a Silicon-on-Insulator Transistor

Electrical Characterization of a Second-gate in a Silicon-on-Insulator Transistor Electrical Characterization of a Second-gate in a Silicon-on-Insulator Transistor Antonio Oblea: McNair Scholar Dr. Stephen Parke: Faculty Mentor Electrical Engineering As an independent double-gate, silicon-on-insulator

More information

SPECIAL REPORT SOI Wafer Technology for CMOS ICs

SPECIAL REPORT SOI Wafer Technology for CMOS ICs SPECIAL REPORT SOI Wafer Technology for CMOS ICs Robert Simonton President, Simonton Associates Introduction: SOI (Silicon On Insulator) wafers have been used commercially as starting substrates for several

More information

www.soiconsortium.org By Xavier CAUCHY, Digital Applications Manager, Soitec xavier.cauchy@soitec.fr with François ANDRIEU, Senior Research Engineer, LETI April 2010 SOI Industry Consortium Questions and

More information

Monolithic Pixel Detector in a 0.15µm SOI Technology

Monolithic Pixel Detector in a 0.15µm SOI Technology Monolithic Pixel Detector in a 0.15µm SOI Technology 2006 IEEE Nuclear Science Symposium, San Diego, California, Nov. 1, 2006 Yasuo Arai (KEK) KEK Detector Technology Project : [SOIPIX Group] Y. Arai Y.

More information

SiNANO-NEREID Workshop:

SiNANO-NEREID Workshop: SiNANO-NEREID Workshop: Towards a new NanoElectronics Roadmap for Europe Leuven, September 11 th, 2017 WP3/Task 3.2 Connectivity RF and mmw Design Outline Connectivity, what connectivity? High data rates

More information

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

Measurement and modelling of specific behaviors in 28nm FD SOI UTBB MOSFETs of importance for analog / RF amplifiers

Measurement and modelling of specific behaviors in 28nm FD SOI UTBB MOSFETs of importance for analog / RF amplifiers Measurement and modelling of specific behaviors in 28nm FD SOI UTBB MOSFETs of importance for analog / RF amplifiers Denis Flandre, Valeriya Kilchytska, Cecilia Gimeno, David Bol, Babak Kazemi Esfeh, Jean-Pierre

More information

Signal Integrity Modeling and Measurement of TSV in 3D IC

Signal Integrity Modeling and Measurement of TSV in 3D IC Signal Integrity Modeling and Measurement of TSV in 3D IC Joungho Kim KAIST joungho@ee.kaist.ac.kr 1 Contents 1) Introduction 2) 2.5D/3D Architectures with TSV and Interposer 3) Signal integrity, Channel

More information

A 2.4-GHz 24-dBm SOI CMOS Power Amplifier with Fully Integrated Output Balun and Switched Capacitors for Load Line Adaptation

A 2.4-GHz 24-dBm SOI CMOS Power Amplifier with Fully Integrated Output Balun and Switched Capacitors for Load Line Adaptation A 2.4-GHz 24-dBm SOI CMOS Power Amplifier with Fully Integrated Output Balun and Switched Capacitors for Load Line Adaptation Francesco Carrara 1, Calogero D. Presti 2,1, Fausto Pappalardo 1, and Giuseppe

More information

First Results of 0.15µm CMOS SOI Pixel Detector

First Results of 0.15µm CMOS SOI Pixel Detector First Results of 0.15µm CMOS SOI Pixel Detector Y. Arai, M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S. Terada, T. Tsuboyama, Y. Unno, H. Ushiroda IPNS, High Energy Accelerator Reserach Organization

More information

INTRODUCTION TO MOS TECHNOLOGY

INTRODUCTION TO MOS TECHNOLOGY INTRODUCTION TO MOS TECHNOLOGY 1. The MOS transistor The most basic element in the design of a large scale integrated circuit is the transistor. For the processes we will discuss, the type of transistor

More information

EUROSOI+- FP of 38 30/06/ FINAL PUBLISHABLE SUMMARY REPORT

EUROSOI+- FP of 38 30/06/ FINAL PUBLISHABLE SUMMARY REPORT EUROSOI+- FP7-216373 3 of 38 30/06/2011 1. FINAL PUBLISHABLE SUMMARY REPORT EUROSOI+- FP7-216373 4 of 38 30/06/2011 EUROSOI+- FP7-216373 5 of 38 30/06/2011 The main and last objective of EUROSOI Network

More information

Stacked-FET linear SOI CMOS SPDT antenna switch with input P1dB greater than

Stacked-FET linear SOI CMOS SPDT antenna switch with input P1dB greater than LETTER IEICE Electronics Express, Vol.9, No.24, 1813 1822 Stacked-FET linear SOI CMOS SPDT antenna switch with input P1dB greater than 40 dbm Donggu Im 1a) and Kwyro Lee 1,2 1 Department of EE, Korea Advanced

More information

3-D Modelling of the Novel Nanoscale Screen-Grid Field Effect Transistor (SGFET)

3-D Modelling of the Novel Nanoscale Screen-Grid Field Effect Transistor (SGFET) 3-D Modelling of the Novel Nanoscale Screen-Grid Field Effect Transistor (SGFET) Pei W. Ding, Kristel Fobelets Department of Electrical Engineering, Imperial College London, U.K. J. E. Velazquez-Perez

More information

Drain. Drain. [Intel: bulk-si MOSFETs]

Drain. Drain. [Intel: bulk-si MOSFETs] 1 Introduction For more than 40 years, the evolution and growth of very-large-scale integration (VLSI) silicon-based integrated circuits (ICs) have followed from the continual shrinking, or scaling, of

More information

FinFET Devices and Technologies

FinFET Devices and Technologies FinFET Devices and Technologies Jack C. Lee The University of Texas at Austin NCCAVS PAG Seminar 9/25/14 Material Opportunities for Semiconductors 1 Why FinFETs? Planar MOSFETs cannot scale beyond 22nm

More information

Design and Analysis of Double Gate MOSFET Devices using High-k Dielectric

Design and Analysis of Double Gate MOSFET Devices using High-k Dielectric International Journal of Electrical Engineering. ISSN 0974-2158 Volume 7, Number 1 (2014), pp. 53-60 International Research Publication House http://www.irphouse.com Design and Analysis of Double Gate

More information

MICROPROCESSOR TECHNOLOGY

MICROPROCESSOR TECHNOLOGY MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 3 Ch.1 The Evolution of The Microprocessor 17-Feb-15 1 Chapter Objectives Introduce the microprocessor evolution from transistors to

More information

Fan-Out Solutions: Today, Tomorrow the Future Ron Huemoeller

Fan-Out Solutions: Today, Tomorrow the Future Ron Huemoeller Fan-Out Solutions: Today, Tomorrow the Future Ron Huemoeller Corporate Vice President, WW RnD & Technology Strategy 1 In the Beginning ewlb 2 Fan Out Packaging Emerges Introduction of Fan Out (ewlb) Marketed

More information

Semiconductor Physics and Devices

Semiconductor Physics and Devices Metal-Semiconductor and Semiconductor Heterojunctions The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of two major types of transistors. The MOSFET is used in digital circuit, because

More information

450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D

450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D 450mm and Moore s Law Advanced Packaging Challenges and the Impact of 3D Doug Anberg VP, Technical Marketing Ultratech SOKUDO Lithography Breakfast Forum July 10, 2013 Agenda Next Generation Technology

More information

Future MOSFET Devices using high-k (TiO 2 ) dielectric

Future MOSFET Devices using high-k (TiO 2 ) dielectric Future MOSFET Devices using high-k (TiO 2 ) dielectric Prerna Guru Jambheshwar University, G.J.U.S. & T., Hisar, Haryana, India, prernaa.29@gmail.com Abstract: In this paper, an 80nm NMOS with high-k (TiO

More information

Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Effect over Bulk MOSFET at 20nm

Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Effect over Bulk MOSFET at 20nm RESEARCH ARTICLE OPEN ACCESS Design & Performance Analysis of DG- for Reduction of Short Channel Effect over Bulk at 20nm Ankita Wagadre*, Shashank Mane** *(Research scholar, Department of Electronics

More information

Semiconductor Materials for Power Electronics (SEMPEL) GaN power electronics materials

Semiconductor Materials for Power Electronics (SEMPEL) GaN power electronics materials Semiconductor Materials for Power Electronics (SEMPEL) GaN power electronics materials Kjeld Pedersen Department of Physics and Nanotechnology, AAU SEMPEL Semiconductor Materials for Power Electronics

More information

Due to the absence of internal nodes, inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible

Due to the absence of internal nodes, inverter-based Gm-C filters [1,2] allow achieving bandwidths beyond what is possible A Forward-Body-Bias Tuned 450MHz Gm-C 3 rd -Order Low-Pass Filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V Supply Joeri Lechevallier 1,2, Remko Struiksma 1, Hani Sherry 2, Andreia Cathelin

More information