SOI technology platforms for 5G: Opportunities of collaboration
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1 SOI technology platforms for 5G: Opportunities of collaboration Dr. Ionut RADU Director, R&D SOITEC MOS AK workshop, Silicon Valley December 6th, 2017
2 Sourcing value from substrate Robert E. White ISBN-13:
3 Agenda 1 Material innovation supporting semiconductor industry 2 RF SOI technology 3 FD SOI technology 4 SOI mix signal platforms for 5G 4 Outlook 3
4 5G era 4
5 Challenges Opportunities for semiconductor innovation 5
6 Material at the heart of semiconductor innovation 6
7 More Moore / More Than Moore More functionalities (Sensing, communication, ) INTEGRATION! Computing, Performance, Power Courtesy of Johann Knechtel, ICCD
8 Material stacking : different configurations Crystal on Crystal (compatible lattice) Amorphous on Amorphous Crystal on Crystal (not compatible lattice) Crystal on Amorphous EPITAXY DEPOSITION (XX-CVD) IMPLANT Smart-Cut TM thin / highly uniform layers 8
9 Revolutionary Smart Cut Industrial maturity (25+ years) Uniformity and layer integrity Donor refreshing Flexibility of material integration 9
10 Material Options Top Si Smart Cut TM versatility Silicon On Insulator Thickness Capabilities Silicon On Sapphire Smart Power SOI TM Piezo On Insulator RF-SOI Photonics SOI PD-SOI InGaN On Sapphire Top Silicon FD-SOI Buried Oxide Base Silicon BOX InP On GaAs 10
11 Engineered substrates supporting our daily drivers 11
12 Agenda 1 Material innovation supporting semiconductor industry 2 RF SOI technology 3 FD SOI technology 4 SOI mix signal platforms for 5G 4 Outlook 12
13 RF-SOI For high efficient mobile communication Power Mono-crystal Top Material Buried Oxide Trap Rich Layer High Resistive Base High resistivity base wafer combined with low mobility trap rich layer just beneath the BOX Low insertion loss (quasi lossless substrate) Performance Cost Reduced crosstalk compared to bulk High linearity compatible with 4G standards Lower cost than MEMS or BSOS based solutions 13
14 RF-SOI - Multiple design platforms for Front End Modules Addressing current needs and new challenges > 10 foundries in HVM mode RF-SOI 45nm RF-SOI 65nm RF-SOI 90nm RF-SOI 0.13um RF-SOI 0.18um Switch DAC PLL + mmw Antenna Tuner Mixers < 6Ghz ADC LNA RF-SOI 0.25um PA Digital 14
15 Enhanced Signal Integrity SOI - esi Trap Rich layer freezes the highly conductive layer at BOX Handle interface Fixed charges Mono-crystal Top Silicon SiO 2 (BOX) Trap rich layer Mobile & Interface trapped charges High Resistivity SI Base 15
16 Substrate s direct impact on die performance esi vs. HR-SOI performance RF Loss Crosstalk Linearity Thermal Conductivity (reducing BOX thickness) High Q Passives 145 nm 25 nm 10 nm Die Size HR-SOI esi 16
17 Agenda 1 Material innovation supporting semiconductor industry 2 RF SOI technology 3 FD SOI technology 4 SOI mix signal platforms for 5G 4 Outlook 17
18 FD-SOI For power efficient & flexible digital computing with easy Analog/RF integration Ultra-thin top silicon & box enabling fully-depleted transistor operation Mono-crystal Top Material 18 Thin Buried Oxide Base (Si) Power Junction capacitance removal Body Bias enabling ULV operation Performance Cost Sub 20nm device scaling Very low mismatch On demand performance through body bias mmwave compatible RF device Immunity to high energy particules Superior analog device behavior compared to bulk Process, temperature & ageing compensation through body bias Lower manufacturing cost for foundry than bulk Lower NRE than FinFET
19 Back-Biasing principle Concept: Bias applied to tune body potential. Body Factor: Efficiency of V T tuning. Technique similar to Bulk AVS FDSOI: Wider range and better efficiency. Effect V T tunning (several decades of I OFF ). Same transistor can give high I on (low V T ) and Low I OFF (high V T ). Back Bias High I ON V T shift Low I OFF P. Flatresse et al. S3S Conference Short Course, 2014 V dd 19
20 SS FF IDDQ Leakage IDDQ EWS/Room Neutron-SER in FT/Mb Very unique features same technology platform mmwave RF-CMOS Ultra Low Voltage Process compensation through body bias Immunity to radiations Leakage limit Untrimmed Performace Boost Leakage spread reduction Trimmed 28nm FD-SOI Source: GF, GTC2017 Source: Sugii,Low Power El. Appl Frequency Source: P. Flatresse, ST, ICICDT17 ST Vendor A ST Vendor A ST ST 65nm 45nm 45nm 28nm 28nm 28nm Bulk Bulk Bulk Bulk Bulk FD-SOI Source: ST, Shanghai FDSOI forum, 2015 Best CMOS mmwave with similar performance to SiGe radios Operation at minimum energy point (<0.4V) 4X less process spread +15% frequency boost 20x Soft Error Rate improvement vs. bulk 20
21 Channel and Back-Gate oxide within starting substrate Ultra-Thin Top Silicon Layer Ultra-Thin Buried Oxide Base Silicon Substrate characteristics Thickness Uniformity Micro-roughness Macro-roughness Electrical properties Defectivity Metal contamination Thickness Uniformity Parasitics charges Integrity (Breakdown voltage) Geometry Bulk Micro Defects Metal contamination Impact on device Electrostatics Variability Mobility Yield Electrostatics Back gate control Variability Reliability Yield + variability All these characteristics are key to control in FD-SOI 21
22 iavt (mv.µm) Material vs device characteristics (supported by TCAD models) Top Si : Thin and uniform top layer is key to maintain good electrostatics and variability: BOX : Thin BOX is key to maintain good electrostatics and body factor: NMOS wafer_1 Tsi=10nm wafer_9 Tsi=12nm wafer_17 Tsi=15nm S (µm²) 10nm 12nm 15nm 22
23 Thickness control ± 1 Atomic Layer! Silicon thickness uniformity is guaranteed to within just a few atomic layers: +5Å Target -5Å Soitec FD-SOI wafer ±5Å ±0.9mm 23
24 iavt (mv.µm) Many different spatial frequencies to consider in FD-SOI SOI Box Handle wafer Wafer to Wafer Thickness Uniformity Within Wafer Within Wafer 10-6 Thickness Uniformity 10-2 Macro roughness 1 Within Wafer Micro roughness µm High Macro Roughness 10 8 Low Macro Roughness S (µm²) Macro-roughness is one of the key parameters for FD-SOI
25 Efficient collaboration with equipment vendors Example of FD-SOI roughness management Enhanced smoothing in high temperature batch anneal technology F.De Crecy CEA/LETI Simulation of silicon smoothing under high temp anneal Unique chip scale thickness measurement developed with HSEB HSEB Baldur tool FD-SOI Local Thickness Variability Within Wafer Uniformity DRM 6s (A) < 3.0 < 3.5 < 4.0 < 4.5 < 5.0 < 5.5 < 6.0 < 6.5 < 7.0 > 7.0 Tool customized with new deposit management for SOI manufacturing New tool redesign ongoing for enhanced flow managment to achieve ultimate FD-SOI roughness & uniformity Collaboration on Differential Reflective Metrology development Full map thickness measurement a critical parameter for FD- SOI 25
26 FD-SOI thickness performance 26
27 FD-SOI : 15nm HVM box scaling demonstrated 27
28 A multi-nodes FD-SOI Product Roadmap Target node 65FD 28FD 22FD 12FD Beyond 12FD Box thick. 15nm 25nm 20nm 15 20nm 20nm FD-SOI substrate Top Si unif Top Si thick. Top Si Mob. ± 1.0 nm 30 nm Si unstrained ± 0.5 nm 12 nm Si unstrained ± 0.5 nm 12 nm Si unstrained ± 0.4 nm 12 nm Si unstrained tbd Pending device Si / SiGe Strained / relaxed Industrial status Prod. Prod. Prod. Dev. R&D 28
29 FD-SOI Multiple Foundry Offering In development FDS 18nm FDX 12nm RF emram FDX 22nm RF emram In production SOTB 65nm FDS 28nm RF emram 29
30 Accelerating FD-SOI Adoption Consumer: a game changer technology for better battery life Automotive : best power efficiency allowing simpler integration and enhanced reliability FD-SOI cuts standard GPS power consumption by 5 to 10 times 30 i.mx reference platform by NXP FD-SOI - Reference technology for ADAS level 3 applications Next generation e- Cockpit solution with full management of car infotainment
31 Agenda 1 Material innovation supporting semiconductor industry 2 RF SOI technology 3 FD SOI technology 4 SOI mix signal platforms for 5G 4 Outlook 31
32 SOI mixed signal platforms for 4G & 5G Mixed signal design & integration options Lower Power Higher Frequency Signal Integrity No junction capacitance Back Bias Ultra low VDD Short Channels Low Device Parasitics Forward Body Bias Low transmission loss High isolation Low harmonics FD-SOI Wide range of digital app. Ultra Low Power IoT Transceivers Low Power analog 5G Front End Module 5G transceivers Radar mmwave (77Ghz) PD-SOI / HR 5G Front End Module RF-SOI / RFeSI 3/4G Front End Module Antenna Switch Antenna Tuner Low Noise Amplifier Power Amplifier 32
33 FD-SOI Technology for 5G mmw Source : GlobalFoundries, Practical MMWave 5G Solutions, J. Jensen, CICC 2017 FD-SOI made with regular FD-SOI 22nm wafer Integration of full Front End Module and transceiver Under evaluation by fabless 33
34 Take-Aways Engineered substrate brings value (i.e. PPAC) to device and electronic circuits SOI substrates are enabling functionalities integration => paradigm shift Smart Cut enables heterogeneous material integration meeting 5G applications requirements Close collaboration and partnership starting at early development phases between technology developers and device and circuit modeling is mandatory to design the 5G products 34
35 Broad innovation: Multi-dimensional, multi-partner Innovation platforms (i.e. 5G) Systems ICs Substrate Device System co-optimization from early R&D Smart Substrates 35
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