Ramya Srinivasan GLOBALFOUNDRIES 22FDX: Tempus Body-Bias Interpolation QoR. April
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1 Ramya Srinivasan GLOBALFOUNDRIES 22FDX: Tempus Body-Bias Interpolation QoR April
2 22FDX: Tempus Body-Bias Interpolation QoR Presenter: Ramya Srinivasan Authors GLOBALFOUNDRIES: Haritez Narisetty and Venkat Ramasubramanian Cadence: Swamy Lokanadham April 11-12, 2017 CDN LIVE: Silicon Valley 2
3 GLOBALFOUNDRIES 22FDx Technology What is 22FDX technology? It is the new 22nm Fully Depleted Siliconon-Insulator (FDSOI) technology from GLOBALFOUNDRIES Delivers FinFET-like performance and powerefficiency at 28nm cost Software-controlled transistor body-biasing for flexible trade-off between performance and power Integrated RF for reduced system cost and back-gate feature to reduce RF power Enables applications across mobile, IoT and RF markets Planar Bulk Transistor Planar FDSOI Transistor with green Insulator layer Effects of Body Biasing in Bulk Transistor and FDSOI Transistor 3
4 Body-biasing Provides Greatest Design Flexibility Forward body-bias (FBB) enables low voltage operation Reverse body-bias (RBB) enables low leakage Dynamic body-biasing enables active tradeoff of performance versus power FDSOI variability is smaller across die due to lower doping effort Improve within die or die-to-die uniformity Post-silicon tuning/trimming -2V to +2V Body-Biasing 4
5 Body-Biasing Power/Performance Trade-off Maximum Performance Operating Mode Forward Body-bias (FBB) Reverse Body-bias (RBB) Minimum Leakage In Standby Mode Max Frequency 5
6 GLOBALFOUNDRIES 22FDX Technology FBB versus RBB Bias voltage is applied to P-well and N-well Reverse Body Bias (RBB) raising VT of device nmos neg. substrate voltage, pmos pos. substrate voltage Forward Body Bias (FBB) lowering VT of device nmos pos. substrate voltage, pmos neg. substrate voltage 6
7 What is body-biasing? A new dimension to design closure Substrate biasing is a low power technique For tuning performance and static power consumption of a device Body-biasing applied through voltage variation on PWELL and NWELL terminal Same implementation can be timed with different Bias voltages resulting in different performance results Different Body-Biasing domains on one chip are enabling new design architectures and design styles Due to the variation in Body Bias as a new variable, now the corners are PVTB (Process/Voltage/Temperature/Body Bias) PVT + BIAS PVTB Library Char + LVF variability Bulk Flow Lib char with BB (Added corners) New Step for 22FDX 7
8 Body-Bias in Design Flow. Concept of 22FDx Body-Bias Trimming FBB Blocks - Design to TT&FF Design Block 1 FBB Block 3 RBB Block 2 FBB Post Silicon TRIM Top VNW = 0 VPW = 0 Slow parts VNW = 0 VPW = 0 VNW=0+ VPW=0- Design implementation performed at TT-FFG corner and STA is done at SSG with FBB to recover silicon dies that land in SSG material. Si Trimming currently focused to meet performance for silicon dies landing on SSG material 8
9 Body-Bias in Design Flow. Concept of 22FDx Body-Bias Trimming RBB Blocks - Design to TT&SS Design Block 1 FBB Block 3 RBB Block 2 FBB Post Silicon TRIM Top VNW = 0 VPW = 0 VNW = 0+ VPW = 0- Fast parts VNW = 0 VPW = 0 RBB Blocks get slower with increase in BB - RBB blocks need to be reverse biased to be able adjust fast/leaky parts to the spec using TRIM 9
10 Design Methodology for BB Trim Process Control Monitor driven BB voltage generator Dynamic: Can use BB optimization on the spot after implementation (Interpolation in Tempus) Block Design to TT & FF VDD VSS Design Chip TRIM-BB-SS VNW, PWN Identify the TRIM-BB to shift SS to TT. Call it TRIM-BB-SS Process Contrrol Monitor BB Gen Signoff/ECO with TRIM-BB-SS (interpolation/lvf), TT (LVF) & FF (LVF) Post silicon TRIM the SS parts with TRIM-BB- SS 10
11 Body-Bias Interpolation in Tempus Body-Bias Flow Library set creation using four libraries on the boundary at different bias-voltages using the command create_library_set Lib1: 0.8v,25c (0v,0v) Lib2: 0.8v,25c (0v,-2v) Lib3: 0.8v,25c (1v,0v) Lib4: 0.8v,25c (1v,-2v) Power domain definition for the supply nets VDD, VNW and VPW Operating condition definition for all the supply nets VDD, VNW, VPW using the command create_op_cond create_op_cond -name op_1 -P 1 -V T 25 -library_file TT_0P80V_0P00V_0P00V_0P00V_25C.lib create_op_cond -name op_2 -P 1 -V T 25 -library_file TT_0P80V_0P00V_0P00V_0P00V_25C.lib create_op_cond -name op_3 -P 1 -V 0.5 -T 25 -library_file TT_0P80V_0P00V_0P00V_0P00V_25C.lib VPW 0,0 VNW 1,0 0,-2 1,-2 11
12 Tempus Body-Bias Interpolation Flow STA Settings Waveform propagation enabled SI analysis turned off PBA Mode LVF libraries Tempus Tool Version: Tempus to Spectre Validation: Bias voltage scaling is validated with spice accuracy correlation for uncoupled path delay Bias scaling can be performed for any point on the surface (yellow points) Blue points are pre-characterized points Both delay and local variation interpolation supported in Tempus Read netlist and link design VNW Library set creation and enable 0,0 bias voltage 1,0 scaling Load UPF (has bias PG info) VPW Update timing and generate reports Tempus 0,-2 1,-2 STA Flowchart 12
13 Testcase Setup Testcase: data engine of 32 bit core Cell-count: 150K (std-cells) Setup Analysis with PBA mode Forward-Bias Mode Placement Utilization: 65% Library: 8T CNRX Metal Stack: 8M layers 13
14 Results-Delay Interpolation Delay Interpolation at VNW:0.5V and VPW: -0.5V Absolute Difference in Data Arrival Time (in ps) Percentage Difference between Tempus and Spectre(in %) Data Arrival Time Comparison between Tempus and Spectre Path ID Data Arrival Time Comparison between Tempus and Spectre Path ID Tempus to Spectre VPW Tempus to Spectre VNW 0,0 1,0 0.5V,-0.5V 0,-2 1,-2 14
15 Results-Delay Interpolation Delay Interpolation at VNW:1.0V and VPW: -1.0V Abolute difference in data arrival time 0,0 1,0 Absolute Difference between Tempus and Spectre (in ps) Path ID Tempus to Spectre 1.0V,-1.0V 0,-2 1,-2 Percentage Difference between Tempus and Spectre (in %) Percentage difference in data arrival time Path ID Tempus to Spectre 15
16 Results Tempus to Monte-Carlo Delay and Variation Interpolation at VNW:0.5V and VPW: -0.5V Monte-Carlo simulations in Spectre with 5000 seed VNW 0,0 1,0 Percentage Difference in Data Arrival Time 0.5V,-0.5V Percentage Difference between Tempus and Spectre (in %) Path ID Tempus to Spectre VPW 0,-2 1,-2 16
17 Conclusion Body-Bias algorithm works accurately in Tempus Good correlation seen between Tempus to Spectre for delay and variation interpolation Some paths see correlation greater that 3%. Work in progress with Cadence to improve correlation for the outliers GLOBALFOUNDRIES will deploy body-bias scaling capability in Tempus in digital reference flows Future Work: GLOBALFOUNDRIES is working with Cadence to include body-bias interpolation capability in upstream flows (Genus/Innovus) and power interpolation in Voltus. 17
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