Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing

Transcription

1 Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas University of Illinois at Urbana-Champaign MICRO-40, Chicago, December 2007

2 Parameter variation: roadblock to scaling Process Variation Temperature Variation Supply Voltage Variation 2

3 Parameter variation: roadblock to scaling Process Variation Temperature Variation Within die (WID) Die-to-die (D2D) 2

4 Parameter variation: roadblock to scaling Proce 1.4 iation Within die (WID Normalized Frequency % 5X 130nm Normalized Leakage (Isb( Isb) [Shekhar Borkar, Intel Corp.] 2

5 Technology scaling faces a major roadblock Process Variation Temperature Variation Threshold Voltage (Vth) Chip frequency Chip leakage power 3

6 Body biasing Well known technique for Vth control A voltage is applied between source/drain and substrate of a transistor Forward body bias (FBB) Vth Freq Leak Reverse body bias (RBB) Vth Freq Leak Key knob to trade off frequency for leakage Frequency BB Leakage power Frequency DVFS Dynamic power 4

7 Body bias design space Space Time Static BB fixed for chip lifetime Dynamic BB changes with T and workload Chip-wide Fine-grain D2D Vth Variation [Intel Xscale] [Intel s 80-core chip] WID Vth Variation [Tschanz et al] D2D Vth Variation T Variation WID Vth Variation T Variation (space and time) 5

8 Body bias design space Space Time Static BB fixed for chip lifetime Dynamic BB changes with T and workload Chip-wide Fine-grain D2D Vth Variation [Intel Xscale] [Intel s 80-core chip] WID Vth Variation S-FGBB [Tschanz et al] D2D Vth Variation T Variation WID Vth Variation D-FGBBn (space and time) 5

9 Outline Background on S-FGBB Dynamic fine-grain body biasing (D-FGBB) Environments Evaluation Conclusions 6

10 Outline Background on S-FGBB Dynamic fine-grain body biasing (D-FGBB) Environments Evaluation Conclusions 7

11 Static fine-grain body biasing [Tschanz et al, ISSCC 2002] Vth variation Fine Grain Body Bias FBB RBB RBB RBB 8 The chip is divided in BB cells Slow cells receive FBB - increase speed Leaky cells receive RBB - save leakage The result is reduced WID variation (delay, power) BB voltages determined at manufacturing Fixed for the lifetime of the chip

12 Frequency binning Bin 1 Frequency Bin 2 Bin 3 Bin 4 High power Leakage power limit Leakage 9

13 Frequency binning Bin 1 Frequency Bin 2 Bin 3 Bin 4 High power Leakage power limit Leakage 9

14 Frequency binning Bin 1 Frequency Bin 2 Bin 3 Bin 4 High power Leakage power limit Leakage 9

15 Frequency binning Bin 1 Frequency Bin 2 Bin 3 Bin 4 High power Leakage power limit Leakage 9

16 Frequency binning Bin 1 Frequency Bin 2 Bin 3 Bin 4 High power Leakage power limit Leakage 9

17 Calibration after manufacturing Calibration conditions (Tcal, Pmax) Calibration takes place at maximum temperature Tcal (burn-in oven) Frequency Forig Original chip Power limit Leakage 10

18 Calibration after manufacturing Calibration conditions (Tcal, Pmax) Calibration takes place at maximum temperature Tcal (burn-in oven) Frequency P <Pmax Forig Original chip Power limit Leakage 10

19 Calibration after manufacturing Calibration conditions (Tcal, Pmax) Calibration takes place at maximum temperature Tcal (burn-in oven) Frequency Fcal P Pmax F cal becomes the chip s frequency Forig Original chip Power limit Leakage 10

20 Outline Background on S-FGBB Dynamic fine-grain body biasing (D-FGBB) Environments Evaluation Conclusions 11

21 Motivation for D-FGBB Significant temperature variation: Space: across different functional units, on chip Time: as the activity factor of the workload changes Between average and worst case conditions (Tcal) D-FGBB can exploit this temperature variation Adapt the body bias to changing conditions 12

22 Motivation for D-FGBB Optimal body bias: The body bias than minimizes leakage power at the target frequency Circuit delay changes with temperature Therefore optimal BB changes with temperature The goal of D-FGBB is to keep the body bias optimal as T changes 13

23 Finding the optimal BB Measure the delay of each BB domain (cell) Delay sampling circuit: CLK Critical Path Replica Phase Detector FBB RBB delay sampling circuit Phase detector - measures delay of critical path replica If slow - FBB signal raised If fast - RBB signal raised 14

24 Applying dynamic fine-grain BB BB is determined based on feedback from delay samples Sample Points RBB FBB FBB RBB AND DEC Local Bias Generator N-CNT D2A NMOS V bb OR INC P-CNT D2A PMOS V bb RBB FBB FBB RBB Body Bias Cell 15

25 Applying dynamic fine-grain BB BB is determined based on feedback from delay samples Sample Points RBB FBB FBB RBB AND DEC Local Bias Generator N-CNT D2A NMOS V bb OR INC P-CNT D2A PMOS V bb RBB FBB FBB RBB Body Bias Cell 15

26 Applying dynamic fine-grain BB BB is determined based on feedback from delay samples Sample Points RBB FBB FBB RBB AND DEC Local Bias Generator N-CNT D2A NMOS V bb OR INC P-CNT D2A PMOS V bb RBB FBB FBB RBB Body Bias Cell 15

27 Applying dynamic fine-grain BB BB is determined based on feedback from delay samples Sample Points RBB FBB FBB RBB AND DEC Local Bias Generator N-CNT D2A NMOS V bb OR INC P-CNT D2A PMOS V bb RBB FBB FBB RBB Body Bias Cell 15

28 Applying dynamic fine-grain BB BB is determined based on feedback from delay samples Sample Points RBB FBB FBB RBB AND DEC Local Bias Generator N-CNT D2A NMOS V bb OR INC P-CNT D2A PMOS V bb RBB FBB FBB RBB Body Bias Cell The BB changes until optimal delay is reached BB stays constant, until T conditions change again 15

29 Outline Background on S-FGBB Dynamic fine-grain body biasing (D-FGBB) Environments Evaluation Conclusions 16

30 D-FGBB environments Operating environments Standard D-FGBB Minimize leakage power at Fcal High performance Maximize average frequency Low Power Minimize leakage power at Forig 17

31 D-FGBB environments Operating environments Standard D-FGBB Minimize leakage power at Fcal High performance Maximize average frequency Low Power Minimize leakage power at Forig 18

32 Standard environment Calibration conditions (Tcal, Pmax) S-FGBB finds and sets Fcal Frequency Fcal Original chip Power limit Leakage 19

33 Standard environment Calibration conditions (Tcal, Pmax) S-FGBB finds and sets Fcal Frequency Fcal Original chip Power limit Leakage 19

34 Standard environment Average conditions (Tavg, Pavg) S-FGBB finds and sets Fcal Frequency Fcal S-FGBB at Tavg Original chip Power limit Leakage 19

35 Standard environment Average conditions (Tavg, Pavg) D-FGBB at Tavg S-FGBB finds and sets Fcal Frequency Fcal S-FGBB at Tavg Original chip Power limit Leakage 19

36 Standard environment Average conditions (Tavg, Pavg) D-FGBB at Tavg S-FGBB finds and sets Fcal Frequency Fcal S-FGBB at Tavg D-FGBB saves leakage power compared to S-FGBB at Fcal Original chip Power limit Leakage 19

37 D-FGBB environments Operating environments Standard D-FGBB Minimize leakage power at Fcal High performance Maximize average frequency Low Power Minimize leakage power at Forig 20

38 High performance Calibration conditions (Tcal, Pmax) Average power Pavg<<Pmax Frequency Fcal S-FGBB at Tcal Original chip Power limit Leakage 21

39 High performance Average conditions (Tavg, Pavg) Average power Pavg<<Pmax Frequency Fcal S-FGBB at Tavg S-FGBB at Tcal Original chip Power limit Leakage 21

40 High performance Favg Average conditions (Tavg, Pavg) D-FGBB Average power Pavg<<Pmax Frequency Fcal S-FGBB at Tavg S-FGBB at Tcal Original chip Power limit Leakage 21

41 High performance Favg Average conditions (Tavg, Pavg) D-FGBB Average power Pavg<<Pmax Frequency Fcal S-FGBB at Tavg S-FGBB at Tcal D-FGBB improves average frequency Original chip Power limit Leakage 21

42 D-FGBB environments Operating environments Standard D-FGBB Minimize leakage power at Fcal High performance Maximize average frequency Low Power Minimize leakage power at Forig 22

43 Low power Average conditions (Tavg, Pavg) The chip runs at its original frequency (Forig) Frequency Fcal Forig Original chip Power limit Leakage 23

44 Low power Average conditions (Tavg, Pavg) The chip runs at its original frequency (Forig) Frequency Fcal Forig D-FGBB S-FGBB Power limit Leakage 23

45 Low power Average conditions (Tavg, Pavg) The chip runs at its original frequency (Forig) Frequency Fcal D-FGBB S-FGBB D-FGBB saves leakage power at Forig Forig Power limit Leakage 23

46 Outline Background on S-FGBB Dynamic fine-grain body biasing (D-FGBB) Environments Evaluation Conclusions 24

47 Evaluation infrastructure Process variation model - VARIUS [ASGI 07] Generate Vth and Leff variation maps for 200 chips SESC - cycle accurate microarchitectural simulator - execution time, dynamic power Mix of SPECint and SPECfp benchmarks HotLeakage, SPICE model - leakage power Hotspot - temperature estimation 25

48 Evaluation parameters 4-core CMP, based on Alpha nm technology, 4GHz Vth variation: σvth/μvth=3-12%, σsys=σrand Leff variation σleff= σvth/2 Vdd=1V, Vth0=250mV, Vbb= ±500mV 26

49 CMP architecture L2 Cache FPQ FPMap IntMap IntQ IntReg FPMul FPAdd FPReg Bpred ICache IntExec LdSTQ ITB DTB DCache CMP 27

50 Body bias granularity We evaluate FGBB at different granularities BB cells per chip Shapes and sizes follow functional units FGBB16 FGBB64 FGBB144 28

51 D-FGBB environments Operating environments Standard D-FGBB Minimize leakage power at Fcal High performance Maximize average frequency Low Power Minimize leakage power at Forig 29

52 D-FGBB reduces leakage 1.15 Frequency D-FGBB144 D-FGBB64 D-FGBB16 D-FGBB1 Leakage reduction 42% 28% S-FGBB144 S-FGBB64 S-FGBB16 S-FGBB1 NoBB D-FGBB reduces leakage significantly More BB cells result in higher frequency and lower leakage Leakage

53 D-FGBB environments Operating environments Standard D-FGBB Minimize leakage power at Fcal High performance Maximize average frequency Low Power Minimize leakage power at Forig 31

54 D-FGBB improves frequency Frequency D-FGBB144 D-FGBB64 D-FGBB16 D-FGBB1 S-FGBB144 S-FGBB64 7% 9% Frequency increase More BB cells result in a higher increase S-FGBB S-FGBB1 NoBB Leakage

55 D-FGBB improves frequency Frequency D-FGBB144 D-FGBB64 D-FGBB16 D-FGBB1 S-FGBB144 S-FGBB64 7% 9% Frequency increase More BB cells result in a higher increase Significant power cost, but still within the power budget S-FGBB S-FGBB1 NoBB 2.5X Leakage

56 D-FGBB environments Operating environments Standard D-FGBB Minimize leakage power at Fcal High performance Maximize average frequency Low Power Minimize leakage power at Forig 33

57 D-FGBB reduces leakage 1.10 Frequency D144 Leakage reduction D64 D16 S144 S64S16 D1 S1 NoBB More BB cells result in higher savings % 10% Leakage

58 Conclusions D-FGBB is more effective than S-FGBB at reducing WID variation: 50% lower leakage 10% higher frequency because D-FGBB adapts to T variation D-FGBB can give architects an additional knob to tradeoff frequency/power Frequency D-FGBB Leakage power 35

59 More in the paper... Details about our variation model A solution for combining D-FGBB with DVFS Estimated overheads of D-FGBB More implementation details 36

60 Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas University of Illinois at Urbana-Champaign MICRO-40, Chicago, December 2007